Obsolete Product(s) - Obsolete Product(s)
TDA7500A
24/40
EXTERNAL MEMORY INTERFACE (EMI) DRAM MODE
Note: 1. n is the number of successive accesses. n = 2, 3, 4, or 6.
DRAM Refresh Timing
Note: 1. Happens when a Refresh Cycle is followed by an Access Cycle.
Characteristics
Timing
Mode
40MHz
Unit
Min. Max.
Page Mode Cycle Time slow
fast
10075 ---- ns
ns
RAS
or RD Assertion to Data Valid slow
fast
--
--
159
109
ns
ns
CAS
Assertion to Data Valid slow
fast
--
--
65
40
ns
ns
Column Address Valid to Data Valid slow
fast
--
--
80
55
ns
ns
CAS
Assertion to Data Active 0 -- ns
RAS
Assertion Pulse Width (Note 1)
(Page Mode Access Only)
slow
fast
264
189
--
--
ns
ns
RAS
Assertion Pulse Width (Single Access Only) slow
fast
164
114
--
--
ns
ns
RAS
or CAS Negation to RAS Assertion slow
fast
120
70
--
--
ns
ns
CAS
Assertion Pulse Width slow
fast
65
40
--
--
ns
ns
Last CAS
Assertion to RAS Negation (Page Mode Access Only) slow
fast
60
35
--
--
ns
ns
Characteristics
Timing
Mode
40MHz
Unit
Min. Max.
RAS
Negation to RAS Assertion slow
fast
143
93
--
--
ns
ns
CAS
Negation to CAS Assertion slow
fast
118
68
--
--
ns
ns
Refresh Cycle Time slow
fast
325
225
--
--
ns
ns
RAS
Assertion Pulse Width slowf
ast
166
116
--
--
ns
ns
RAS
Negation to RAS Assertion for Refresh Cycle (Note 1) slow
fast
120
70
--
--
ns
ns
CAS
Assertion to RAS Assertion on Refresh Cycle 18 -- ns
RAS
Assertion to CAS Negation on Refresh Cycle slow
fast
160
110
--
--
ns
ns
RAS
Negation to CAS Assertion on a Refresh Cycle slow
fast
114
64
--
--
ns
ns
CAS
Negation to Data Not Valid 0 -- ns
Obsolete Product(s) - Obsolete Product(s)
