TDA7500A Datasheet TDA7500A, TDA7500ATR | P28-P30

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C TIMING

Figure 16. Definition of Timing for the I

C BUS.

SPDIF TIMING

Symbol Parameter Test Condition

Standard Mode

C BUS

Fast Mode

C BUS

Unit

Min. Max. Min. Max.

SCL

SCLl clock frequency 0 100 0 400 kHz

BUF

Bus free between a STOP and

Start Condition

4.7 – 1.3 – µs

HD:STA

Hold time (repeated) START

condition. After this period, the

first clock pulse is generated

4.0 – 0.6 – µs

LOW

LOW period of the SCL clock 4.7 – 1.3 – µs

HIGH

HIGH period of the SCL clock 4.0 – 0.6 – µs

SU:STA

Set-up time for a repeated start

condition

4.7 – 0.6 – µs

HD:DAT

DATA hold time 0 – 0 0.9 µs

Rise time of both SDA and SCL

signals

Cb in pF – 1000 20+

0.1C

300 ns

Fall time of both SDA and SCL

signals

Cb in pF – 300 20+

0.1C

300 ns

SU;STO

Set-up time for STOP condition 4 – 0.6 – µs

SU:DAT

Data set-up time 250 -- -- 100 ns

Capacitive load for each bus line – 400 – 400 pF

Symbol Parameter Test Condition Min. Typ. Max. Unit

SPVL AC input level 0.2 0.5 3.3 Vpp

SPIR Input impedance

@ 1 kHz

–6–kΩ

SPHYS Hysteresis of input – 40 – mV

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TDA7500A

FUNCTIONAL DESCRIPTION

The TDA7500A IC broken up into two distinct blocks. One block contains the two DSP Cores and their associ-

ated peripherals. The other contains the ADC, DAC and the RDS filter, demodulator and decoder.

24-BIT DSP CORE

The two DSP cores are used to process the audio and FM/AM data, coming from the ADC, either any kind of

digital data coming via SPDIF or SAI. After the digital signal processing these data are sent to the DAC for an-

alog conversion. Functions such as volume, tone, balance, and fader control, as well as spatial enhancement

and general purpose signal processing may be performed by the DSP0. When FM/AM mode is selected, DSP1

is fully devoted to AM/FM processing. Nevertheless it can be used for any kind of different application, when a

different input source is selected.

Some capabilities of the DSPs are listed below:

■

Single cycle multiply and accumulate with convergent rounding and condition code generation

■

2 x 56-bit Accumulators

■

Double precision multiply

■

Scaling and saturation arithmetic

■

48-bit or 2 x 24-bit parallel moves

■

64 interrupt vector locations

■

Fast or long interrupts possible

■

Programmable interrupt priorities and masking

■

8 each of Address Registers, Address Offset Registers and Address Modulo Registers

■

Linear, Reverse Carry, Multiple Buffer Modulo, Multiple Wrap-around Modulo address arithmetic

■

Post-increment or decrement by 1 or by offset, Index by offset, predecrement address

■

Repeat instruction and zero overhead DO loops

■

Hardware stack capable of nesting combinations of 7 DO loops or 15 interrupts/subroutines

■

Bit manipulation instructions possible on all registers and memory locations, also Jump on bit test

■

4 pin serial debug interface

■

Debug ccess to all internal registers, buses and memory locations

■

5 word deep program address history FIFO

■

Hardware and software breakpoints for both program and data memory accesses

■

Debug Single stepping, Instruction injection and Disassembly of program memory

DSP PERIPHERALS

There are a number of peripherals that are tightly coupled to the two DSP Cores. Same of the peripherals are

connected to DSP 0 others are connected to DSP1.

■

5.5k x 24-Bit Program RAM for DSP0

■

1k x 24-Bit X-Data RAM for DSP0

■

1k x 24-Bit Y-Data RAM for DSP0

■

2k x 24-Bit Program RAM for DSP1

■

1k x 24-Bit X-Data RAM for DSP1

■

1k x 24-Bit Y-Data RAM for DSP1

■

Serial Audio Interface (SAI)

■

SPDIF receiver with sampling rate conversion

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■

I2C and SPI interface

■

XCHG Interface for DSP to DSP communication

■

External Memory Interface (DRAM/SRAM) for time-delay and traffic information

■

Double Debug Port

DATA AND PROGRAM MEMORY

Both DSP0 and DSP1 have Data and Program memories attached to them. Each of the memories are described

below and it is implied that there are two of each type, one set connected to DSP0 and the other to DSP1. The

only exception is the case of the P-RAM where DSP1 has a 2048 x 24-Bit PRAM and DSP0 has a 5.5K x 24-

Bit PRAM.

1024 x 24-Bit X-RAM (XRAM)

This is a 1024 x 24-Bit Single Port SRAM used for storing coefficients. The 16-Bit XRAM address, XABx(15:0)

is generated by the Address Generation Unit of the DSP core. The 24-Bit XRAM Data, XDBx(23:0), may be writ-

ten to and read from the Data ALU of the DSP core. The XDBx Bus is also connected to the Internal Bus Switch

so that it can be routed to and from all peripheral blocks.

1024 x 24 Bit Y-RAM (YRAM)

This is a 512 x 24-Bit Single Port SRAM used for storing coefficients. The 16-Bit address, YABx(15:0) is gener-

ated by the Address Generation Unit of the DSP core. The 24-Bit Data, YDBx(23:0), is written to and read from

the Data ALU of the DSP core. The YDBx Bus is also connected to the Internal Bus Switch so that it can be

routed to and from other blocks.

2048 x 24-Bit Program RAM (PRAM 5.5K x 24-bit for DSP0)

This is a 2048 x 24-Bit Single Port SRAM used for storing and executing program code. The 16-Bit PRAM Ad-

dress, PABx(15:0) is generated by the Program Address Generator of the DSP core for Instruction Fetching,

and by the AGU in the case of the Move Program Memory (MOVEM) Instruction. The 24-Bit PRAM Data (Pro-

gram Code), PDBx(23:0), can only be written to using the MOVEM instruction. During instruction fetching the

PDBx Bus is routed to the Program Decode Controller of the DSP core for instruction decoding.

512 x 24-Bit Bootstrap ROM (PROM 256 x 24 Bit for DSP1)

This is a 512 x 24-Bit factory programmed Boot ROM used for storing the program sequence and for initializing

the DSP. Essentially this consists of reading the data via I2C, SPI or EMI interface and store it in PRAM, XRAM,

YRAM, and/or external DRAM.

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TDA7500A

Mfr. #:

Buy TDA7500A

Manufacturer:

STMicroelectronics

Description:

IC PROCESSOR AM/FM DGTL 100-TQFP

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TDA7500A

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