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TDA7500A

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P40
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TDA7500A
EXTERNAL MEMORY INTERFACE (EMI) SRAM MODE
Figure 12. External Memory Interface SRAM Read Cycle.
Figure 13. External Memory Interface SRAM Write Cycle.
Characteristics
40MHz
Unit
Min. Max.
Address Valid and CS
Assertion Pulse Width 89 -- ns
Address Valid to RD
or WR Assertion 23 -- ns
RD
or WR Assertion Pulse Width 45 -- ns
RD
or WR Negation to RD or WR Assertion 39 -- ns
RD
or WR Negation to Address not Valid 5 -- ns
Address Valid to Input Data Valid -- 72 ns
RD
Assertion to Input Data Valid -- 35 ns
RD
Negation to Data Not Valid (Data Hold Time) 0 -- ns
Address Valid to WR
Negation 73 -- ns
Data Setup Time to WR
Negation 32 -- ns
Data Hold Time from WR
Negation 5 -- ns
WR
Assertion to Data Valid -- 18 ns
WR
Negation to Data High-Z (Note 1) -- 23 ns
WR
Assertion to Data Active 5 -- ns
add. [7:0]
data
add. [13:8]
SRA_D
[7:0]
SRA_D
[13:8]
ALE
DRD
add. [7:0]
data
add. [13:8]
SRA
[7:0]
SRA
[13:8]
ALE
DWR
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Figure 14. DRAM Read Cycle.
Figure 15. DRAM Write Cycle.
DRA [8:0]
Row address 1 Column address 1
Column address 2 Row address 2
RAS
CAS
DRD
nibble 1 nibble 2
DRD [3:0]
Row address 1
Column address 1 Column address 2 Row address 2
DWR
CAS
DRA [8:0]
RAS
nibble 1
nibble 2
DRD[3:0]
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TDA7500A
SAMPLE RATE CONVERTER
F
sin
/F
sout
= 1 (44.1KHz)
RDS TIMING
The RDS block adhere to the timings defined by the RDS standard EN50067. More information are also available in the dedicated Appllication
Note.
Symbol Parameter Test Condition Min. Typ. Max. Unit
THD+N Total Harmonic Distortion +
Noise
20Hz to 20kHz, Full Scale, 16 bit inp.
-98 dB
20Hz to 20kHz, Full Scale, 20 bit inp.
-101 dB
1 kHz Full Scale, 16 bit inp. -98 dB
10 kHz Full Scale, 16 bit inp. -98 dB
1 kHz Full Scale, 20 bit inp. -109 dB
10 kHz Full Scale, 20 bit inp -102 dB
DR Dynamic Range
1 kHz -60 dB - 16 bit inp.,A-Weighted
98 dB
1 kHz -60 dB - 20 bit inp.,A-Weighted
120 dB
IPD Interchannel Phase Deviation 0
Degree
f
c
Cutoff Frequency @ -3 dB 20 Hz
R
p
Pass Band Ripple from 0 to 20kHz -0.05 +0.05 dB
R
s
Stopband Attenuation @24.1kHz -105 dB
T
g
Group Delay Fsout = 44.1 kHz 612 µs
F
ratio
F
sin
/ F
sout
0.7 1.05
Symbol Parameter Test Condition Min. Typ. Max. Unit
F
crystal
Crystal Frequency First mode - 8.55 - MHz
Second mode - 8.664 - MHz
t
bclk
RDS SPI Bit Clock (T
DSP is the period of the dsp core)
3T
DSP
--ns
t
dis
SPI Disable time between 2
transfers
3T
DSP
--ns
Obsolete Product(s) - Obsolete Product(s)
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TDA7500A

Mfr. #:
Buy TDA7500A
Manufacturer:
STMicroelectronics
Description:
IC PROCESSOR AM/FM DGTL 100-TQFP
Lifecycle:
New from this manufacturer.
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