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TDA7500A
SAI INTERFACE
Figure 1. SAI Timings
Note T
DSP
= dsp master clock cycle time = 1/F
DSP
Figure 2. SAI protocol when RLRS=0; RREL=0; RCKP=1; RDIR=0
Timing Description Value Unit
t
sckr
Minimum Clock Cycle 4T
DSP
ns
t
dt
SCKR active edge to data out valid 10 ns
t
lrs
LRCK setup time 5 ns
t
lrh
LRCK hold time 5 ns
t
sdid
SDI setup time 15 ns
t
sdih
SDI hold time 15 ns
t
sckph
Minimum SCK high time 0.35 t
sckr
ns
t
sckpl
Minimum SCK low time 0.35 t
sckr
ns
SDI0-3
LRCKR
SCKR
(RCKP=0)
t
lrh
t
sdis
t
sdih
t
lrs
t
sckpl
t
sckph
Valid
Valid
t
dt
t
sckr
LEFT
RIGHT
LSB(n-1) MSB(word n)
MSB-1 (n)
MSB-2 (n)
LRCKR (#68)
SCKR (#67)
SDI0,1,2 (#62, #63, #64)
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TDA7500A
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Figure 3. SAI protocol when RLRS=1; RREL=0; RCKP=1; RDIR=1.
Figure 4. SAI protocol when RLRS=0; RREL=0; RCKP=0; RDIR=0.
Figure 5. SAI protocol when RLRS=0; RREL=1; RCKP=1; RDIR=0.
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TDA7500A
SPI INTERFACES
Figure 6. SPI Clocking scheme.
10 WORDS MAIN MICRO SPI
Symbol Description Min Value Unit
MASTER
t
sclk
Clock Cycle 12T
DSP
ns
t
dtr
Sclk edge to MOSI valid 40 ns
t
misosetup
MISO setup time 16 ns
t
misohold
MISO hold time 4 ns
t
sclkh
SCK high time 0.5t
sclk
ns
t
sclkl
SCK high low 0.5t
sclk
ns
SLAVE
t
sclk
Clock Cycle 12T
DSP
ns
t
dtr
Sclk edge to MOSI valid 40 ns
t
mosisetup
MOSI setup time 16 ns
t
mosihold
MOSI hold time 4 ns
t
sclkh
SCK high time 0.5t
sclk
ns
t
sclkl
SCK high low 0.5t
sclk
ns
DISPLAY SPI (different timings)
MASTER
t
sclk
Clock Cycle 6T
DSP
ns
SLAVE
t
sclk
Clock Cycle 6T
DSP
ns
SCLKD, SCLKM (#6, #10)
(CPOL=0, CPHA=0)
MISOM, MOSIM (#7, #8)
MISOD, MOSID (#11, #12)
SSM, SSD (#9, #13)
(CPOL=0, CPHA=1)
(CPOL=1, CPHA=0)
(CPOL=1, CPHA=1)
Internal Strobe for Data Capture
MSB 6 5 4 3 2 1 LSB
SCLKD, SCLKM (#6, #10)
SCLKD, SCLKM (#6, #10)
SCLKD, SCLKM (#6, #10)
Obsolete Product(s) - Obsolete Product(s)

TDA7500A

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
IC PROCESSOR AM/FM DGTL 100-TQFP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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