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TDA7500A
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P24
P25-P27
P28-P30
P31-P33
P34-P36
P37-P39
P40-P40
Obsolete Product(s) - Obsolete Product(s)
19/
40
TDA7500A
SAI
INTE
RFACE
Figu
re 1
.
S
AI
Tim
in
gs
No
te
T
DSP
= dsp maste
r clock cyc
le
time =
1/F
DSP
Figure
2
. SAI
protoc
ol when RLRS=0;
RREL=0; RCKP=1;
RDIR=0
Timing
Des
cript
ion
V
alu
e
Unit
t
sckr
Minimum Clock Cy
cle
4T
DSP
ns
t
dt
SCKR active edg
e to d
ata o
ut valid
10
ns
t
lrs
LRCK setu
p time
5
ns
t
lr
h
LRCK hold
time
5
ns
t
sdi
d
SDI setup
time
15
ns
t
sdi
h
SDI hold tim
e
15
ns
t
sckp
h
Minimum SCK
high
time
0.35 t
sckr
ns
t
sckp
l
Minimum SCK
low time
0.35
t
sckr
ns
SDI0-3
LRCK
R
SCKR
(RCKP=0)
t
lrh
t
sdis
t
sdih
t
lrs
t
sckpl
t
sckph
V
ali
d
V
ali
d
t
dt
t
sckr
LEFT
RIG
H
T
LSB(n-
1)
MSB(
word n)
MSB-
1
(n)
MSB-
2
(n)
LRCKR (#68)
SCKR
(#67)
SDI0,1,2 (#62,
#63, #64)
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
TDA7500A
20/40
Figure
3
. SAI
protoc
ol when RLRS=1;
RREL=0; RCKP=1;
RDIR=1.
Figure
4
. SAI
protoc
ol when RLRS=0;
RREL=0; RCKP=0;
RDIR=0.
Figure
5
. SAI
protoc
ol when RLRS=0;
RREL=1; RCKP=1;
RDIR=0.
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
21/
40
TDA7500A
SPI I
N
TER
FAC
ES
Figure 6. SPI Clocking sch
eme.
10 WORDS M
AIN
MICRO SP
I
Symb
ol
Descript
ion
Min V
a
lue
Unit
MASTER
t
sclk
Clock Cycle
12T
DSP
ns
t
dt
r
Sclk edge
to MO
SI valid
40
ns
t
misosetup
MISO setu
p time
16
ns
t
misoh
old
MISO hold
time
4
n
s
t
sclk
h
SCK high time
0.
5t
sclk
ns
t
sclk
l
SCK high low
0.5t
sclk
ns
SLA
VE
t
sclk
Clock Cycle
12T
DSP
ns
t
dt
r
Sclk edge
to MO
SI valid
40
ns
t
mo
si
set
up
MOSI setu
p time
16
ns
t
mosih
old
MOSI hold
time
4
n
s
t
sclk
h
SCK high time
0.
5t
sclk
ns
t
sclk
l
SCK high low
0.5t
sclk
ns
DISPLA
Y SPI (dif
ferent t
iming
s)
MASTER
t
sclk
Clock Cycle
6T
DSP
ns
SLA
VE
t
sclk
Clock Cycle
6T
DSP
ns
SCLK
D
,
SCLKM
(#6,
#10
)
(C
POL=0,
C
PHA
=0)
MISO
M
, MOS
IM (
#7, #
8)
MI
SOD
,
MOSI
D (#11
, #1
2)
SSM,
SSD (#9,
#
13)
(C
POL=0,
C
PHA
=1)
(C
POL=1,
C
PHA
=0)
(C
POL=1,
C
PHA
=1)
In
te
r
n
a
l
St
r
o
be
fo
r
D
ata
C
a
p
tu
r
e
MSB
6
5
4
3
2
1
LSB
SCLK
D
,
SCLK
M (#6,
#10
)
SCLK
D
,
SCLK
M (#6,
#10
)
SCLK
D
,
SCLKM
(#6,
#10
)
Obsolete Product(s) - Obsolete Product(s)
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P24
P25-P27
P28-P30
P31-P33
P34-P36
P37-P39
P40-P40
TDA7500A
Mfr. #:
Buy TDA7500A
Manufacturer:
STMicroelectronics
Description:
IC PROCESSOR AM/FM DGTL 100-TQFP
Lifecycle:
New from this manufacturer.
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