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TDA7500A

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P40
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14 CLKIN I Clock Input pin (Input). Clock from external digital audio source
to synchronize the internal PLL.
15 AVDD Supply pin dedicated to the PLL.
16 XTI I Crystal Oscillator Input (Input). External Clock Input or crystal
Oscillator input.
17 XTO O Crystal Oscillator Output (Output). Crystal Oscillator output
drive.
18 AGND Ground pin dedicated to the PLL.
19 RDSINT/DSP1_GPIO4 O RDS bit/block interrupt (Output)/General Purpose I/O (Input/
Output). Provides an interrupt to the main micro. Optionally it
can be used as general purpose I/O controlled by DSP1.
20 RDSARI_SCK/DSP1_GPIO3 O SPI Bit Clock (Input)/ARI indicator (Output)/General Purpose I/O
(Input/Output). If SPI interface is enabled, behaves as SPI bit
clock. Optionally it provides the ARI indication bit. Optionally it
can be used as general purpose I/O controlled by DSP1.
21 RDSQAL_SO/DSP1_GPIO2 O SPI Slave Output Serial Data (Output)/RDS Bit Quality (Output)/
General Purpose I/O (Input/Output). If SPI is enabled, behaves
as Serial Data Output. Optionally it provides the RDS serial data
quality information. Optionally it can be used as general purpose
I/O controlled by DSP1.
22 RDSDAT_SI/DSP1_GPIO1 I SPI Slave Input Serial Data (Input)/RDS Bit Data (Output)/
General Purpose I/O (Input/Output). If SPI is enabled, behaves
as Serial Data Input. Optionally it provides the RDS serial data
stream. Optionally it can be used as general purpose I/O
controlled by DSP1.
23 RDSCLK_SS/DSP1_GPIO0 I SPI Chip Select (Input)/RDS Bit Clock (Output)/General
Purpose I/O (Input/Output). If SPI is enabled, behaves as Chip
Select line for SPI bus. Optionally it provides the 1187.5Hz RDS
Bit Clock. Optionally it can be used as general purpose I/O
controlled by DSP1.
24 INT I External interrupt line (Input). When this line is asserted low, the
DSP may be interrupted. Acts as IRQA line of DSP0 core.
25 CGND1 Ground pin dedicated to the digital circuitry.
26 CVDD1 Supply pin dedicated to the digital circuitry.
27 SCRCCD I SPDIF Input 1 (Input). Stereo SPDIF input to connect a digital
audio source like a CD.
28 SCRMD I SPDIF Input 2 (Input). Stereo SPDIF input to connect a digital
audio source like a MD.
29 DSRA<7> I/O DSP SRAM Data Lines<7> (Input/Output). When in SRAM
Mode this pin act as the EMI data line 7.
30 DSRA<6> I/O DSP SRAM Data Lines<6> (Input/Output). When in SRAM
Mode this pin act as the EMI data line 6.
N° Name Type Description
PIN DESCRIPTION
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TDA7500A
31 DSRA<5> I/O DSP SRAM Data Lines<5> (Input/Output). When in SRAM
Mode this pin act as the EMI data line 5.
32 DSRA<4> I/O DSP SRAM Data Lines<4> (Input/Output). When in SRAM
Mode this pin act as the EMI data line 4.
33 DSRA<3> I/O DSP SRAM Data Lines<3> (Input/Output)/DSP DRAM Data
Line<3>(Input/Output). This pin act as the EMI data line 3 in
both SRAM Mode and DRAM Mode.
34 DSRA<2> I/O DSP SRAM Data Lines<2> (Input/Output)/DSP DRAM Data
Line<2>(Input/Output). This pin act as the EMI data line 2 in
both SRAM Mode and DRAM Mode.
35 DSRA<1> I/O DSP SRAM Data Lines<1> (Input/Output)/DSP DRAM Data
Line<1>(Input/Output). This pin act as the EMI data line 1 in
both SRAM Mode and DRAM Mode.
36 DSRA<0> I/O DSP SRAM Data Lines<0> (Input/Output)/DSP DRAM Data
Line<0>(Input/Output). This pin act as the EMI data line 0 in
both SRAM Mode and DRAM Mode.
37 SRA<0> O DSP SRAM Address Line<0> (Output)/DSP DRAM Address
Line<0> (Output). This pin acts as the EMI address line 0 in both
SRAM Mode and DRAM Mode
38 SRA<1> O DSP SRAM Address Line<1> (Output)/DSP DRAM Address
Line<1> (Output). This pin acts as the EMI address line 1 in both
SRAM Mode and DRAM Mode
39 SRA<2> O DSP SRAM Address Line<2> (Output)/DSP DRAM Address
Line<2> (Output). This pin acts as the EMI address line 2 in both
SRAM Mode and DRAM Mode
40 SRA<3> O DSP SRAM Address Line<3> (Output)/DSP DRAM Address
Line<3> (Output). This pin acts as the EMI address line 3 in both
SRAM Mode and DRAM Mode
41 SRA<4> O DSP SRAM Address Line<4> (Output)/DSP DRAM Address
Line<4> (Output). This pin acts as the EMI address line 4 in both
SRAM Mode and DRAM Mode
42 SRA<5> O DSP SRAM Address Line<5> (Output)/DSP DRAM Address
Line<5> (Output). This pin acts as the EMI address line 5 in both
SRAM Mode and DRAM Mode
43 SRA<6> O DSP SRAM Address Line<6> (Output)/DSP DRAM Address
Line<6> (Output). This pin acts as the EMI address line 6 in both
SRAM Mode and DRAM Mode
44 SRA<7> O DSP SRAM Address Line<7> (Output)/DSP DRAM Address
Line<7> (Output). This pin acts as the EMI address line 7 in both
SRAM Mode and DRAM Mode
45 SRA<8> O DSP SRAM Address Line<8> (Output)/DSP DRAM Address
Line<8> (Output). This pin acts as the EMI address line 8 in both
SRAM Mode and DRAM Mode
N° Name Type Description
PIN DESCRIPTION
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46 SRA<9> O DSP SRAM Address Line<9> (Output)/DSP DRAM Address
Line<9> (Output). This pin acts as the EMI address line 9 in both
SRAM Mode and DRAM Mode
47 SRA<10> O DSP SRAM Address Line<10> (Output)/DSP DRAM Address
Line<10> (Output). This pin acts as the EMI address line 10 in
both SRAM Mode and DRAM Mode
48 SRA<11> O DSP SRAM Address Line<11> (Output)/DSP DRAM Address
Line<11> (Output). This pin acts as the EMI address line 11 in
both SRAM Mode and DRAM Mode
49 SRA<12> O DSP SRAM Address Line<12> (Output)/DSP DRAM Address
Line<12> (Output). This pin acts as the EMI address line 12 in
both SRAM Mode and DRAM Mode
50 CGND2 Ground pin dedicated to the digital circuitry.
51 CVDD2 Supply pin dedicated to the digital circuitry.
52 SRA<13> O DSP SRAM Address Line<13> (Output)/DSP DRAM Address
Line<13> (Output). This pin act as the EMI address line 13 in
both SRAM Mode and DRAM Mode.
53 SRA<14> O DSP SRAM Address Line<14> (Output)/DSP DRAM Address
Line<14> (Output). This pin act as the EMI address line 14 in
both SRAM Mode and DRAM Mode.
54 SRA<15> O DSP SRAM Address Line<15> (Output)/DSP DRAM Address
Line<15> (Output). This pin act as the EMI address line 15 in
both SRAM Mode and DRAM Mode.
55 SRA<16>/DSP0_GPIO8 O DSP SRAM Address Line<16> (Output)/DSP DRAM Address
Line<16> (Output)/General Purpose I/O (Input/Output). This pin
acts as the EMI address line 16 in both SRAM Mode and DRAM
Mode. Optionally it can be used as general purpose I/O
controlled by DSP0. After reset the state of this pin is read by the
boot SW to select the boot mode (Refer to HW/SW maual).
56 DWR O DSP SRAM Write Enable (Output)/DRAM Write Enable
(Output). This pin serves as the write enable for the EMI in both
DRAM and SRAM Mode (active low). To be connected to R/W of
the RAM.
57 DRD O DSP SRAM Read Enable(Output)/DRAM Read Enable (Output).
This pin serves as the read enable for the EMI in both DRAM
and SRAM Mode (active low). To be connected to R/W of the
RAM.
58 CASALE O DSP DRAM Column Address Strobe (Output). When in DRAM
Mode this pin acts as the column address strobe.
59
SDO<2>/SRA<17>/DSP1_GPIO<8>
O SAI Outputs (Output)/EMI SRAM Address Line<17> (Output)/
General Purpose I/O (Input/Output). One stereo channel SAI
data output in SAI mode. EMI address line 17 in SRAM Mode.
Optionally it can be used as a general purpose I/O.
N° Name Type Description
PIN DESCRIPTION
(continued)
Obsolete Product(s) - Obsolete Product(s)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P40

TDA7500A

Mfr. #:
Buy TDA7500A
Manufacturer:
STMicroelectronics
Description:
IC PROCESSOR AM/FM DGTL 100-TQFP
Lifecycle:
New from this manufacturer.
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