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TDA7500A

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P40
Obsolete Product(s) - Obsolete Product(s)
13/40
TDA7500A
69 DSP1 Debug: DBOUT output
DSP1: GPIO10 input
DSP1: GPIO10 output
X
1 1 1 output 4mA PP
input 5VT
output 4mA PP
After boot in
debug mode
70 DSP1 Debug: DBIN input
DSP1 : OS10 output
DSP1: GPIO11 input
DSP1: GPIO11 output
X
X X X input 5VT
output 4mA PP
input 5VT
output 4mA PP
After boot in
debug mode
71 DSP1 Debug: DBCK input
DSP1 : OS11 output
DSP1: GPIO9 input
DSP1: GPIO9 output
X
X X X input 5VT
output 4mA PP
input 5VT
output 4mA PP
After boot in
debug mode
72 DSP1 Debug: DBRQN input X X X X input 5VT After boot in
debug mode
73 DSP0 Debug: DBOUT output
DSP0: GPIO10 input
DSP0: GPIO10 output
X
1 1 1 output 4mA PP
input 5VT
output 4mA PP
After boot in
debug mode
74 DSP0 Debug: DBIN input
DSP0 : OS00 output
DSP0: GPIO11 input
DSP0: GPIO11 output
X
X X X input 5VT
output 4mA PP
input 5VT
output 4mA PP
After boot in
debug mode
75 DSP0 Debug: DBCK input
DSP0 : OS01 output
DSP0: GPIO9 input
DSP0: GPIO9 output
X
X X X input 5VT
output 4mA PP
input 5VT
output 4mA PP
After boot in
debug mode
76 DSP0 Debug: DBRQN input X X X X input 5VT
77 GND2 supply
78 VDD2 supply
79 ADC<0>input X X X X analog input
80 ADC<1>input X X X X analog input
81 ADC<2>input X X X X analog input
82 ADC<3>input X X X X analog input
83 ADC: S2DREF input Substrate biasing
connected to GND
84 ADC: ADCVDDREF input voltage reference connect 47µF
electolytic and
100nF Ceramic
parallel to
ADCGND
85 ADC: REF<2> input voltage reference connect 100µF
electolytic and
100nF Ceramic
parallel to
ADCGND
Pin
#
Function
Reset
State
After Boot
I/O Comments
SPI
I
2
C
EMI
I/O DEFINITION AND STATUS
(continued)
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
TDA7500A
14/40
Output
PP
: Push-Pull/
OD
: Open-Drain
5VT
input: TTL Five Volt Tolerant Input - Schmitt-trigger for all inputs.
86 ADC: REF<1> input voltage reference connect 47µF
electolytic and
100nF Ceramic
parallel to
ADCGND
87 ADC: REF<0> input voltage reference connect 47µF
electolytic and
100nF Ceramic
parallel to
ADCGND
88 ADCVDD ADC power supply
89 ADCGND ADC ground
90 DAC<0> output X X X X analog output
91 DAC<1> output X X X X analog output
92 DAC<2> output X X X X analog output
93 DAC<3> output X X X X analog output
94 DAC<4> output X X X X analog output
95 DAC<5> output X X X X analog output
96 DAC: REF<2> input voltage reference connect 47µF
electolytic and
100nF Ceramic
parallel to
DACGND
97 DAC: REF<1> input voltage reference connect 47µF
electolytic and
100nF Ceramic
parallel to
DACGND
(It can be
connected to
Pin100)
98 DAC: REF<0> input voltage reference connect to
DACGND
(It can be
connected to
Pin99)
99 DACGND DAC ground
100 DACVDD DAC power supply
Pin
#
Function
Reset
State
After Boot
I/O Comments
SPI
I
2
C
EMI
I/O DEFINITION AND STATUS
(continued)
Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s)
15/40
TDA7500A
PIN CONNECTION
(Top view)
RECOMMENDED DC OPERATING CONDITIONS
POWER CONSUMPTION
Note: 45MHz internal DSP clock, 4ADC and 6DAC enabled.
PLL CHARACTERISTICS
Note: 1. Depending on VCO output frequency.
2. F
dsp
= F
vco
/2 when PLL is running
Symbol Parameter Test Condition Min. Typ. Max. Unit
V
DD
3.3V Digital Power Supply Voltage 3.15 3.3 3.45 V
V
CC
3.3V Analog Power Supply Voltage
3.15 3.3 3.45 V
Symbol Parameter Test Condition Min. Typ. Max. Unit
I
dd
Total Maximum Current
power supply @ 3.3V and T
j
= 125°C
450 490 mA
Symbol Parameter Test Condition Min. Typ. Max. Unit
Lock Time (note1)
power supply @ 3.3V and T
j
= 125°C
3ms
F
VCO
VCO Frequency (note 2) 70 140 MHz
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
TESTEN
TESTSE
NRESET
SCKM
MOSIM
MISOM
SSM
SCKD
MOSID
MISOD
SSD
AVDD
XTI
XTO
CLKIN
AGND
RDSINT
RDSARI_SCK
RDSDAT_SI
RDSQAL_SO
RDSCLK_SS
INT
CGND1
CVDD1
SCRCCD
DSRA<7>
DSRA<6>
DSRA<5>
DSRA<4>
DSRA<3>
DSRA<2>
DSRA<1>
DSRA<0>
SRA<1>
SRA<0>
SRA<2>
SRA<3>
SRA<4>
SRA<5>
SRA<6>
SRA<7>
SRA<8>
SRA<9>
SRA<10>
SRA<11>
SRA<12>
SCRCMD
CGND2
DBCK0OS01
DBIN0OS00
DBOUT0
DBRQN1
DBCK1_OS11
DBIN1_OS10
DBOUT1
LRCKR
SCKR
LRCKT
SCKT
SDI0
SDI1/SRA<21>/RAS
SDI2 / SRA<20>
SDO0 / SRA<19>
SDO1 / SRA<18>
SDO2 / SRA<17>
CASALE
DRD
DWR
SRA<15>
SRA<14>
SRA<13>
CVDD2
SRA<16>
DACREF0
DACREF1
DACREF2
DACVDD
DACGND
DAC5
DAC4
DAC3
DAC2
DAC1
DAC0
ADCREF0
ADCREF1
ADCREF2
S2DREF
ADCVDDREF
ADC3
ADC1
ADC2
ADC0
ADCGND
ADCVDD
GND2
VDD2
DBRQN0
DSP0 GPIO0
DSP0 GPIO2
DSP0 GPIO1
DSP0 GPIO3
DSP0 GPIO4
DSP0 GPIO6
DSP0 GPIO5
DSP0 GPIO7
DSP1 GPIO4
DSP1 GPIO3
DSP1 GPIO1
DSP1 GPIO2
DSP1 GPIO0
DSP0 GPIO9
DSP0 GPIO11
DSP0 GPIO10
DSP0 GPIO8
DSP1 GPIO5
DSP1 GPIO6
DSP1 GPIO7
DSP1 GPIO8
DSP1 GPIO9
DSP1 GPIO11
DSP1 GPIO10
SRCCDC
CODEC
Test
IIC/SPI master
SPI displa
y
PLL oscillator
RDS
SPDIF
EMI
SAI
Debu
g
DSP1
Debu
g
DSP0
GND1
VDD1
EMI
SPDIF
OD
OD
OD
OD
OD
OD: 5V tolerant Open Drain Output
Obsolete Product(s) - Obsolete Product(s)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P40

TDA7500A

Mfr. #:
Buy TDA7500A
Manufacturer:
STMicroelectronics
Description:
IC PROCESSOR AM/FM DGTL 100-TQFP
Lifecycle:
New from this manufacturer.
Delivery:
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