12
FN6451.0
March 30, 2007
Real Time Clock Registers
Addresses [00h to 06h]
RTC REGISTERS (SC, MN, HR, DT, MO, YR, DW)
These registers depict BCD representations of the time. As
such, SC (Seconds) and MN (Minutes) range from 0 to 59,
HR (Hour) can either be a 12-hour or 24-hour mode, DT
(Date) is 1 to 31, MO (Month) is 1 to 12, YR (Year) is 0 to 99,
and DW (Day of the Week) is 0 to 6.
The DW register provides a Day of the Week status and uses
three bits DW2 to DW0 to represent the seven days of the
week. The counter advances in the cycle 0-1-2-3-4-5-6-0-1-
2-… The assignment of a numerical value to a specific day
of the week is arbitrary and may be decided by the system
software designer. The default value is defined as “0”.
24 HOUR TIME
If the MIL bit of the HR register is “1”, the RTC uses a
24-hour format. If the MIL bit is “0”, the RTC uses a 12-hour
format and HR21 bit functions as an AM/PM indicator with a
“1” representing PM. The clock defaults to 12-hour format
time with HR21 = “0”.
LEAP YEARS
Leap years add the day February 29 and are defined as those
years that are divisible by 4. Years divisible by 100 are not leap
years, unless they are also divisible by 400. This means that
the year 2000 is a leap year and the year 2100 is not. The
ISL12021 does not correct for the leap year in the year 2100.
Control and Status Registers (CSR)
Addresses [07h to 0Fh]
The Control and Status Registers consist of the Status
Register, Interrupt and Alarm Register, Analog Trimming and
Digital Trimming Registers.
Status Register (SR)
The Status Register is located in the memory map at
address 07h. This is a volatile register that provides either
control or status of RTC failure (RTCF), Battery Level
Monitor (LBAT85, LBAT75), alarm trigger, Daylight Saving
Time, crystal oscillator enable and temperature conversion
in progress bit.
BUSY BIT (BUSY)
Busy Bit indicates temperature sensing is in progress. In this
mode, Alpha, Beta and ITRO registers are disabled and
cannot be accessed.
OSCILLATOR FAIL BIT (OSCF)
Indicates oscillator stopped.
DAYLIGHT SAVING TIME CHANGE BIT (DSTADJ)
DSTADJ is the Daylight Saving Time Adjusted Bit. It
indicates the daylight saving time adjustment has happened.
DSTADJ is reset to 0 upon power up. If DST event happens
(at either the beginning or the end of DST), DSTADJ will be
set to 1. A read of the SR will reset the DSTADJ, or it will be
automatically reset on the following month.
ALARM BIT (ALM)
These bits announce if the alarm matches the real time clock.
If there is a match, the respective bit is set to “1”. This bit can
be manually reset to “0” by the user or automatically reset by
enabling the auto-reset bit (see ARST bit). A write to this bit in
the SR can only set it to “0”, not “1”. An alarm bit that is set by
an alarm occurring during an SR read operation will remain
set after the read operation is complete.
LOW V
DD
INDICATOR BIT (LV
DD
VDD)
Indicates V
DD
dropped below the pre-selected trip level.
(Brown Out Mode). The Trip points for Brown Out levels are
selected by three bits V
DD
Trip2, V
DD
Trip1 and V
DD
Trip0 in
PWR_V
DD
registers.
LOW BATTERY INDICATOR 85% BIT (LBAT85)
Indicates battery level dropped below the pre-selected trip
levels (85% of battery voltage). The trip points are selected
by three bits: VB85Tp2, VB85Tp1 and VB85Tp0 in the
PWR_VBAT registers.
LOW BATTERY INDICATOR 75% BIT (LBAT75)
Indicates battery level dropped below the pre-selected trip
levels (75% of battery voltage). The trip points are selected
by three bits VB75Tp2, VB75Tp1 and VB75Tp0 in the
PWR_VBAT registers.
REAL TIME CLOCK FAIL BIT (RTCF)
This bit is set to a “1” after a total power failure. This is a read
only bit that is set by hardware (ISL12021 internally) when
the device powers up after having lost all power (defined as
V
DD
= 0V and V
BAT
= 0V). The bit is set regardless of
whether V
DD
or V
BAT
is applied first. The loss of only one of
the supplies does not set the RTCF bit to “1”. The first valid
write to the RTC section after a complete power failure
resets the RTCF bit to “0” (writing one byte is sufficient).
Interrupt Control Register (INT)
AUTOMATIC RESET BIT (ARST)
This bit enables/disables the automatic reset of the ALM,
LVDD, LBAT85, and LBAT75 status bits only. When ARST
bit is set to “1”, these status bits are reset to “0” after a valid
read of the respective status register (with a valid STOP
TABLE 2. STATUS REGISTER (SR)
ADDR 7 6 5 4 3 2 1 0
07h BUSY OSCF DSTDJ ALM LVDD LBAT85 LBAT75 RTCF
TABLE 3. INTERRUPT CONTROL REGISTER (INT)
ADDR7 6 5 4 3210
08h ARST WRTC IM FOBATB FO3 FO2 FO1 FO0
ISL12021
