OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

ISL12021CVZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
19
FN6451.0
March 30, 2007
TEMP Registers (TEMP)
The temperature sensor produces an analog voltage output
and is input to an A/D converter which outputs a 10-bit
temperature value in degrees Kelvin. The output is coded to
produce greater resolution for the temperature control.
TK07:00 are the LSBs of the code, and TK09:08 are the
MSBs of the code. The output code can be converted to
degrees Centigrade by first converting from binary to
decimal and then subtracting 369d.
The practical range for the temp sensor register output is
from 658d to 908d, or -40°C to +85°C.
The TSE bit must be set to “1” to enable temperature
sensing.
User Registers (accessed by using Slave
Address 1010111x)
Addresses [00h to 7Fh]
These registers are 128 bytes of battery-backed user SRAM.
I
2
C Serial Interface
The ISL12021 supports a bi-directional bus oriented
protocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as the
receiver. The device controlling the transfer is the master
and the device being controlled is the slave. The master
always initiates data transfers and provides the clock for
both transmit and receive operations. Therefore, the
ISL12021 operates as a slave device in all applications.
All communication over the I
2
C interface is conducted by
sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (See
Figure 7). On power up of the ISL12021, the SDA pin is in
the input mode.
All I
2
C interface operations must begin with a START
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL12021 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met (See
Figure 7). A START condition is ignored during the power-up
sequence.
All I
2
C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (See Figure 7). A STOP condition at the end of
a read operation or at the end of a write operation to memory
only places the device in its standby mode.
An acknowledge (ACK) is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (See Figure 8).
The ISL12021 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL12021 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation.
TABLE 22.
76543210
TK0L TK07 TK06 TK05 TK04 TK03 TK02 TK01 TK00
TK0M000000TK09TK08
Temperature in °C [(TK <9:0>)/2] - 369=
(EQ. 1)
FIGURE 7. VALID DATA CHANGES, START AND STOP CONDITIONS
SDA
SCL
START
DATA DATA
STOP
STABLE CHANGE
DATA
STABLE
ISL12021
20
FN6451.0
March 30, 2007
Device Addressing
Following a start condition, the master must output a Slave
Address Byte. The 7 MSBs are the device identifier. These bits
are “1101111” for the RTC registers and:1010111” for the User
SRAM.
The last bit of the Slave Address Byte defines a read or write
operation to be performed. When this R/W
bit is a “1”, then a
read operation is selected. A “0” selects a write operation
(refer to Figure 10).
After loading the entire Slave Address Byte from the SDA bus,
the ISL12021 compares the device identifier and device select
bits with “1101111” or “1010111”. Upon a correct compare, the
device outputs an acknowledge on the SDA line.
Following the Slave Byte is a one byte word address. The word
address is either supplied by the master device or obtained
from an internal counter. On power up the internal address
counter is set to address 00h, so a current address read starts
at address 00h. When required, as part of a random read, the
master must supply the 1 Word Address Bytes as shown in
Figure 12.
In a random read operation, the slave byte in the “dummy write”
portion must match the slave byte in the “read” section. For a
random read of the Control/Status Registers, the slave byte
must be “1101111x” in both places.
Write Operation
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL12021 responds with an ACK. At this time, the I
2
C
interface enters a standby state.
Read Operation
A Read operation consists of a three byte instruction
followed by one or more Data Bytes (See Figure 12). The
master initiates the operation issuing the following
sequence: a START, the Identification byte with the R/W
bit
set to “0”, an Address Byte, a second START, and a second
Identification byte with the R/W
bit set to “1”. After each of
the three bytes, the ISL12021 responds with an ACK. Then
FIGURE 8. ACKNOWLEDGE RESPONSE FROM RECEIVER
FIGURE 9. BYTE WRITE SEQUENCE (SLAVE ADDRESS FOR CSR SHOWN)
SDA OUTPUT FROM
TRANSMITTER
SDA OUTPUT FROM
RECEIVER
81 9
START ACK
SCL FROM
MASTER
HIGH IMPEDANCE
HIGH IMPEDANCE
S
T
A
R
T
S
T
O
P
IDENTIFICATION
BYTE
DATA
BYTE
A
C
K
SIGNALS FROM
THE MASTER
SIGNALS FROM
THE ISL12021
A
C
K
10011
A
C
K
WRITE
SIGNAL AT SDA
0000111
ADDRESS
BYTE
FIGURE 10. SLAVE ADDRESS, WORD ADDRESS, AND DATA
BYTES
SLAVE
ADDRESS BYTE
D7 D6 D5 D2D4 D3 D1 D0
A0A7 A2A4 A3 A1
DATA BYTE
A6 A5
1
10
1
1
1
R/W
1
WORD ADDRESS
ISL12021
21
FN6451.0
March 30, 2007
the ISL12021 transmits Data Bytes as long as the master
responds with an ACK during the SCL cycle following the
eighth bit of each byte. The master terminates the read
operation (issuing a STOP condition) following the last bit of
the last Data Byte (See Figure 12).
The Data Bytes are from the memory location indicated by
an internal pointer. This pointers initial value is determined
by the Address Byte in the Read operation instruction, and
increments by one during transmission of each Data Byte.
After reaching the memory location 13h, the pointer “rolls
over” to 00h, and the device continues to output data for
each ACK received.
Application Section
Battery Backup Details
Note that any input signal conditioning circuitry that is added
in regular operation or battery backup should have minimum
supply current drain, or have the capability to be put in a low
power standby mode. Op Amps such as the EL8176 have
low normal supply current (50µA) and standby power drain
(3µA
), so can be used in battery backup applications.
Oscillator Crystal Requirements
The ISL12021 uses a standard 32.768kHz crystal. Either
through hole or surface mount crystals can be used.
Table 23 lists some recommended surface mount crystals
and the parameters of each. This list is not exhaustive and
other surface mount devices can be used with the ISL12021
if their specifications are very similar to the devices listed.
The crystal should have a required parallel load capacitance
of 12.5pF and an equivalent series resistance of less than
50k. The crystal’s temperature range specification should
match the application. Many crystals are rated for -10°C to
+60°C (especially through hole and tuning fork types), so an
appropriate crystal should be selected if extended
temperature range is required.
Layout Considerations
The crystal input at X1 has a very high impedance, and
oscillator circuits operating at low frequencies such as
32.768kHz are known to pick up noise very easily if layout
precautions are not followed. Most instances of erratic
clocking or large accuracy errors can be traced to the
susceptibility of the oscillator circuit to interference from
adjacent high speed clock or data lines. Careful layout of the
RTC circuit will avoid noise pickup and insure accurate
clocking.
Figure 11 shows a suggested layout for the ISL12021 device
using a surface mount crystal. Two main precautions should
be followed:
• Do not run the serial bus lines or any high speed logic
lines in the vicinity of the crystal. These logic level lines
can induce noise in the oscillator circuit to cause
misclocking.
• Add a ground trace around the crystal with one end
terminated at the chip ground. This will provide termination
for emitted noise in the vicinity of the RTC device.
TABLE 23. SUGGESTED SURFACE MOUNT CRYSTALS
MANUFACTURER PART NUMBER
Citizen CM200S
Epson MC-405, MC-406
Raltron RSM-200S
SaRonix 32S12
Ecliptek ECPSM29T-32.768K
ECS ECX-306
Fox FSM-327
FIGURE 11. SUGGESTED LAYOUT FOR ISL12021 AND
CRYSTAL
FIGURE 12. READ SEQUENCE (CSR SLAVE ADDRESS SHOWN)
SIGNALS
FROM THE
MASTER
SIGNALS FROM
THE SLAVE
SIGNAL AT
SDA
S
T
A
R
T
IDENTIFICATION
BYTE WITH
R/W
=0
ADDRESS
BYTE
A
C
K
A
C
K
0
S
T
O
P
A
C
K
1
IDENTIFICATION
BYTE WITH
R/W
= 1
A
C
K
S
T
A
R
T
LAST READ
DATA BYTE
FIRST READ
DATA BYTE
A
C
K
101 1111
101
11
11
ISL12021
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

ISL12021CVZ

Mfr. #:
Buy ISL12021CVZ
Manufacturer:
Renesas / Intersil
Description:
IC RTC CLK/CALENDAR I2C 14-TSSOP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet