ISL12021CVZ Datasheet ISL12021CVZ | P7-P9

FN6451.0

March 30, 2007

Serial Data (SDA)

SDA is a bi-directional pin used to transfer data into and out

of the device. It has an open drain output and may be ORed

with other open drain or open collector outputs. The input

buffer is always active (not gated) in normal mode.

An open drain output requires the use of a pull-up resistor.

The output circuitry controls the fall time of the output signal

with the use of a slope controlled pull-down. The circuit is

designed for 400kHz I

C interface speeds. It is disabled

when the backup power supply on the V

BAT

pin is activated.

VDD, GND

Chip power supply and ground pins. The device will operate

with a power supply from VDD = 2.7V to 5.5VDC. A 0.1µF

capacitor is recommended on the VDD pin to ground.

LVRSET (Low Voltage Reset)

Brown Out Reset Mode. The pin provides an interrupt signal

output. This signal notifies a host processor that the V

level has dropped below pre-programmed level, normally

85% of nominal V

. The brownout trip level is

programmable via a control register. It is an open drain

active low output.

Functional Description

Power Control Operation

The power control circuit accepts a V

and a V

BAT

input.

Many types of batteries can be used with Intersil RTC

products. For example, 3.0V or 3.6V Lithium batteries are

appropriate, and battery sizes are available that can power

the ISL1202x for up to 10 years. Another option is to use a

Super Capacitor for applications where V

is interrupted

for up to a month. See the “Application Section” on page 21

for more information.

Normal Mode (V

) to Battery Backup Mode

BAT

)

To transition from the VDD to VBAT mode, both of the

following conditions must be met:

Condition 1:

< V

BAT

- V

BATHYS

where V

BATHYS

≈ 50mV

Condition 2:

< V

TRIP

where V

TRIP

≈ 2.2V

Battery Backup Mode (V

BAT

) to Normal Mode

)

The ISL12021 device will switch from the V

BAT

to V

mode

when one

of the following conditions occurs:

Condition 1:

> V

BAT

+ V

BATHYS

where V

BATHYS

≈ 50mV

Condition 2:

> V

TRIP

+ V

TRIPHYS

where V

TRIPHYS

≈ 30mV

These power control situations are illustrated in Figure 3 and

Figure 4.

The I

C bus is deactivated in battery backup mode to reduce

power consumption. Aside from this, all RTC functions are

operational during battery backup mode. Except for SCL and

SDA, all the inputs and outputs of the ISL12021 are active

during battery backup mode unless disabled via the control

The device Time Stamps the switchover from V

to V

BAT

and V

BAT

to V

, and the time is stored in T

SV2B

and

SB2V

registers respectively. If multiple V

power down

sequences occur before status is read, the earliest V

BAT

power down time is stored and the most recent V

BAT

to V

time is stored.

Temperature conversion and compensation can be enabled

in battery backup mode. Bit BTSE in the BETA register

controls this operation as described in that register section.

Power Failure Detection

The ISL12021 provides a Real Time Clock Failure Bit

(RTCF) to detect total power failure. It allows users to

determine if the device has powered up after having lost all

power to the device (both V

and V

BAT

- V

BATHYS

BAT

+ V

BATHYS

BATTERY BACKUP

MODE

TRIP

2.2V

1.8V

FIGURE 3. BATTERY SWITCHOVER WHEN V

BAT

< V

TRIP

FIGURE 4. BATTERY SWITCHOVER WHEN V

BAT

> V

TRIP

BAT

TRIP

+ V

TRIPHYS

BATTERY BACKUP

MODE

TRIP

3.0V

2.2V

ISL12021

FN6451.0

March 30, 2007

Brown Out Detection

The ISL12021 monitors the V

level continuously and

provides warning if the V

level drops below the prescribed

levels. There are five (5) levels that could be selected for the

trip level. Typically set at the 85% of nominal V

level. The

Real Time Clock Power Brown Out Bit ( LVDD) is set once

the V

level drops below the trip point. The LVRST output

becomes active when the Power Brown Out Bit is set.

When the V

power is re-established and is above the

85%V

+ 50mV trip point, the V

PBM

0 is set. The LVDD bit

is reset once it is read by the CPU. Note: The I

C comm link

remains active unless the Battery V

TRIP

levels are reached.

Battery Level Monitor

The ISL12021 has a built in warning feature once the Back

Up battery level drops first to 85% and then to 75% of the

battery’s nominal VBAT level. When the battery voltage

drops to between 85% and 75%, the LBAT85 bit is set in the

status register. When the level drops below 75%, both

LBAT85 and LBAT75 bits are set in the status register.

There is a Battery Timestamp Function available. Once the

is low enough to enable switchover to the battery, the

RTC time/date are written into the TSVTB register. This

information can be read from the TSVTB registers to

discover the point in time of the V

powerdown. If there are

multiple powerdown cycles before reading these registers,

the first values stored in these registers will be retained.

These registers will hold the original powerdown value until

they are cleared by writing “00h” to each register.

Low Power Mode

The normal power switching of the ISL12021 is designed to

switch into battery backup mode only if the V

power is

lost. This will ensure that the device can accept a wide range

of backup voltages from many types of sources while reliably

switching into backup mode. Another mode (called Low

Power Mode) is available to allow direct switching from V

to V

BAT

without requiring V

to drop below V

TRIP

. Since

the additional monitoring of V

vs V

TRIP

is no longer

needed, that circuitry is shut down and less power is used

while operating from V

. Power savings are typically

600nA at V

= 5V. Low Power Mode is activated via the

BSW bit in the control and status registers.

Low Power Mode is useful in systems where V

is normally

higher than V

BAT

at all times. The device will switch from

to V

BAT

when V

drops below V

BAT

, with about 50mV

of hysteresis to prevent any switchback of V

after

switchover. In a system with V

= 5V and backup lithium

battery of V

BAT

= 3V, Low Power Mode can be used.

However, it is not recommended to use Low Power Mode in

a system with V

= 3.3V ±10%, V

BAT

≥ 3.0V, and when

there is a finite I-R voltage drop in the V

line.

Real Time Clock Operation

The Real Time Clock (RTC) uses an external 32.768kHz

quartz crystal to maintain an accurate internal representation

of second, minute, hour, day of week, date, month, and year.

The RTC also has leap-year correction. The clock also

corrects for months having fewer than 31 days and has a bit

that controls 24 hour or AM/PM format. When the ISL12021

powers up after the loss of both V

and V

BAT

, the clock will

not begin incrementing until at least one byte is written to the

clock register.

Single Event and Interrupt

The alarm mode is enabled via the MSB bit. Choosing single

event or interrupt alarm mode is selected via the IM bit. Note

that when the frequency output function is enabled, the

alarm function is disabled.

The standard alarm allows for alarms of time, date, day of

the week, month, and year. When a time alarm occurs in

single event mode, an IRQ

pin will be pulled low and the

alarm status bit (ALM) will be set to “1”.

The pulsed interrupt mode allows for repetitive or recurring

alarm functionality. Hence, once the alarm is set, the device

will continue to alarm for each occurring match of the alarm

and present time. Thus, it will alarm as often as every minute

(if only the nth second is set) or as infrequently as once a

year (if at least the nth month is set). During pulsed interrupt

mode, the IRQ

pin will be pulled low for 250ms and the alarm

status bit (ALM) will be set to “1”.

The ALM bit can be reset by the user or cleared

automatically using the auto reset mode (see ARST bit). The

alarm function can be enabled/disabled during battery

backup mode using the FOBATB bit. For more information

on the alarm, please see “ALARM Registers (10h to 15h)” on

page 16.

Frequency Output Mode

The ISL12021 has the option to provide a clock output signal

using the F

OUT

open drain output pin. The frequency output

mode is set by using the FO bits to select 15 possible output

frequency values from 1/32Hz to 32kHz. The frequency

output can be enabled/disabled during battery backup mode

using the FOBATB bit.

General Purpose User SRAM

The ISL12021 provides 128 bytes of user SRAM. The SRAM

will continue to operate in battery backup mode. However, it

should be noted that the I

C bus is disabled in battery

backup mode.

C Serial Interface

The ISL12021 has an I

C serial bus interface that provides

access to the control and status registers and the user

SRAM. The I

C serial interface is compatible with other

industry I

C serial bus protocols using a bi-directional data

signal (SDA) and a clock signal (SCL).

ISL12021

FN6451.0

March 30, 2007

Oscillator Compensation

The ISL12021 provides both initial timing correction and

temperature correction due to variation of the crystal

oscillator. Analog and Digital trimming control is provided for

initial adjustment, and a temperature compensation function

is provided to automatically correct for temperature drift of

the crystal. Initial values for the temperature coefficient

(ALPHA) and crystal capacitance (BETA) are required for

best accuracy. The function can be enabled/disabled at any

time and can be used in battery mode as well.

The battery-backed registers are accessible following a

slave byte of “1101111x” and reads or writes to addresses

[00h:13h]. The defined addresses and default values are

described in the Table 1. The battery backed general

purpose SRAM has a different slave address (1010111x), so

it is not possible to read/write that section of memory while

accessing the registers.

The contents of the registers can be modified by performing

a byte or a page write operation directly to any register

address.

The registers are divided into 8 sections. They are:

1. Real Time Clock (7 bytes): Address 00h to 06h.

2. Control and Status (9 bytes): Address 07h to 0Fh.

3. Alarm (6 bytes): Address 10h to 15h.

4. Time Stamp for Battery Status (5 bytes): Address 16h to

1Ah.

5. Time Stamp for VDD Status (5 bytes): Address 1Bh to

1Fh.

6. Day Light Saving Time (8 bytes): 20h to 27h.

7. TEMP (2 bytes): 28h to 29h

8. Scratch Pad (6 bytes): Address 2Ah to 2Fh.

Write capability is allowable into the RTC registers (00h to

06h) only when the WRTC bit (bit 6 of address 08h) is set to

“1”. A multi-byte read or write operation is limited to one

section per operation. Access to another section requires a

new operation. A read or write can begin at any address

within the section.

A register can be read by performing a random read at any

address at any time. This returns the contents of that register

location. Additional registers are read by performing a

sequential read. For the RTC and Alarm registers, the read

instruction latches all clock registers into a buffer, so an

update of the clock does not change the time being read. At

the end of a read, the master supplies a stop condition to

end the operation and free the bus. After a read, the address

remains at the previous address +1 so the user can execute

a current address read and continue reading the next

It is not necessary to set the WRTC bit prior to writing into

the control and status, alarm, and user SRAM registers.

ISL12021

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24

ISL12021CVZ

Mfr. #:

Buy ISL12021CVZ

Manufacturer:

Renesas / Intersil

Description:

IC RTC CLK/CALENDAR I2C 14-TSSOP

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ISL12021CVZ