13
FN6451.0
March 30, 2007
condition). When the ARST is cleared to “0”, the user must
manually reset the ALM, LVDD, LBAT85, and LBAT75 bits.
WRITE RTC ENABLE BIT (WRTC)
The WRTC bit enables or disables write capability into the
RTC Timing Registers. The factory default setting of this bit
is “0”. Upon initialization or power up, the WRTC must be set
to “1” to enable the RTC. Upon the completion of a valid
write (STOP), the RTC starts counting. The RTC internal
1Hz signal is synchronized to the STOP condition during a
valid write cycle.
INTERRUPT/ALARM MODE BIT (IM)
This bit enables/disables the interrupt mode of the alarm
function. When the IM bit is set to “1”, the alarm will operate
in the interrupt mode, where an active low pulse width of
250ms will appear at the IRQ
pin when the RTC is triggered
by the alarm as defined by the alarm registers (0Ch to 11h).
When the IM bit is cleared to “0”, the alarm will operate in
standard mode, where the IRQ
pin will be set low until the
ALM status bit is cleared to “0”.
FREQUENCY OUTPUT AND INTERRUPT BIT (FOBATB)
This bit enables/disables the F
OUT
and IRQ pins during
battery backup mode (i.e. V
BAT
power source active). When
the FOBATB is set to “1” the F
OUT
and IRQ pins are
disabled during battery backup mode. This means that both
the frequency output and alarm output functions are
disabled. When the FOBATB is cleared to “0”, the F
OUT
and
IRQ
pins are enabled during battery backup mode. Note that
the open drain F
OUT
and IRQ pins will need a pullup to the
battery voltage to operate in battery backup mode.
FREQUENCY OUT CONTROL BITS (FO <3:0>)
These bits enable/disable the frequency output function and
select the output frequency at the F
OUT
pin. See Table 5 for
frequency selection. .
POWER SUPPLY CONTROL REGISTER (PWR_VDD)
Clear Time Stamp Bit (CLRTS)
This bit clears Time Stamp V
DD
to Battery (TSV2B) and
Time Stamp Battery to V
DD
Registers (TSB2V). The default
setting is 0 (CLRTS = 0) and the Enabled setting is 1
(CLRTS = 1)
V
DD
Brown Out Trip Voltage BITS (VDDTrip)<2:0
These bits set the 6 trip levels for the V
DD
alarm, indicating
that V
DD
has dropped below a preset level, in this event, the
LVDD bit in the Status Register is set to “1”. See Table 6.
Battery Voltage Trip Voltage Register (PWR_VBAT)
This register controls the trip points for the two VBAT alarms,
with levels set to approximately 85% and 75% of the nominal
battery level.
TABLE 4.
IM BIT INTERRUPT/ALARM FREQUENCY
0 Single Time Event Set By Alarm
1 Repetitive/Recurring Time Event Set By Alarm
TABLE 5. FREQUENCY SELECTION OF FOUT PIN
FREQUENCY,
FOUT UNITS FO3 FO2 FO1 FO0
0 Hz0 000
32768 Hz 0 0 0 1
4096 Hz 0 0 1 0
1024 Hz 0 0 1 1
64 Hz0 100
32 Hz0 101
16 Hz0 110
8Hz0111
4Hz1000
2Hz1001
1Hz1010
1/2 Hz 1 0 1 1
1/4 Hz 1 1 0 0
1/8 Hz 1 1 0 1
1/16 Hz 1 1 1 0
1/32 Hz 1 1 1 1
ADDR 7 6 5 4 3 2 1 0
09h CLRTS 0 0 0 0 V
DD
Trip2 V
DD
Trip1 V
DD
Trip0
TABLE 6. VDD TRIP LEVELS
V
DD
Trip2 V
DD
Trip1 V
DD
Trip0
TRIP
VOLTAGE
(V)
0 0 0 2.295
0 0 1 2.550
0 1 0 2.805
0 1 1 3.060
1 0 0 4.250
1 0 1 4.675
TABLE 7.
ADDR 7 6 543210
0Ah BSW 0 VB85
Tp2
VB85
Tp1
VB85
Tp0
VB75
Tp2
VB75
Tp1
VB75
Tp0
TABLE 5. FREQUENCY SELECTION OF FOUT PIN (Continued)
FREQUENCY,
FOUT UNITS FO3 FO2 FO1 FO0
ISL12021
