22
FN6451.0
March 30, 2007
In addition, it is a good idea to avoid a ground plane under
the X1 and X2 pins and the crystal, as this will affect the load
capacitance and therefore the oscillator accuracy of the
circuit. If the F
OUT
pin is used as a clock, it should be routed
away from the RTC device as well. The traces for the VBAT
and VDD pins can be treated as a ground, and should be
routed around the crystal.
Super Capacitor Backup
The ISL12021 device provides a VBAT pin which is used for
a battery backup input. A Super Capacitor can be used as an
alternative to a battery in cases where shorter backup times
are required. Since the battery backup supply current
required by the ISL12021 is extremely low, it is possible to
get months of backup operation using a Super Capacitor.
Typical capacitor values are a few µF to 1F or more
depending on the application.
If backup is only needed for a few minutes, then a small
inexpensive electrolytic capacitor can be used. For extended
periods, a low leakage, high capacity Super Capacitor is the
best choice. These devices are available from such vendors
as Panasonic and Murata. The main specifications include
working voltage and leakage current. If the application is for
charging the capacitor from a +5V ±5% supply with a signal
diode, then the voltage on the capacitor can vary from ~4.5V
to slightly over 5.0V. A capacitor with a rated WV of 5.0V
may have a reduced lifetime if the supply voltage is slightly
high. The leakage current should be as small as possible.
For example, a Super Capacitor should be specified with
leakage of well below 1µA. A standard electrolytic capacitor
with DC leakage current in the microamps will have a
severely shortened backup time.
Following are some examples with equations to assist with
calculating backup times and required capacitance for the
ISL12021 device. The backup supply current plays a major
part in these equations, and a typical value was chosen for
example purposes. For a robust design, a margin of 30%
should be included to cover supply current and capacitance
tolerances over the results of the calculations. Even more
margin should be included if periods of very warm
temperature operation are expected.
Example 1. Calculating Backup Time Given
Voltages and Capacitor Value
In Figure 13, use C
BAT
= 0.47F and V
DD
= 5.0V. With
V
DD
= 5.0V, the voltage at V
BAT
will approach 4.7V as the
diode turns off completely. The ISL12021 is specified to
operate down to V
BAT
= 1.8V. The capacitance
charge/discharge equation is used to estimate the total
backup time:
Rearranging gives
C
BAT
is the backup capacitance and dV is the change in
voltage from fully charged to loss of operation. Note that
I
TOT
is the total of the supply current of the ISL12021 (I
BAT
)
plus the leakage current of the capacitor and the diode, I
LKG
.
In these calculations, I
LKG
is assumed to be extremely small
and will be ignored. If an application requires extended
operation at temperatures over +50°C, these leakages will
increase and hence reduce backup time.
Note that I
BAT
changes with V
BAT
almost linearly. This
allows us to make an approximation of I
BAT
, using a value
midway between the two endpoints. The typical linear
equation for I
BAT
vs V
BAT
is:
Using this equation to solve for the average current given 2
voltage points gives:
Combining with Equation 3 gives the equation for backup
time:
where
C
BAT
= 0.47F
V
BAT2
= 4.7V
V
BAT1
= 1.8V
I
LKG
= 0 (assumed minimal)
Solving Equation 5 for this example, I
BATAVG
= 4.387E-7A
t
BACKUP
= 0.47*(2.9)/4.38E-7 = 3.107E6s
Since there are 86,400 seconds in a day, this corresponds to
35.96 days. If the 30% tolerance is included for capacitor
and supply current tolerances, then worst case backup time
would be:
I = C
BAT
*dV/dT
(EQ. 2)
dT = C
BAT
*dV/I
TOT
to solve for backup time.
(EQ. 3)
I
BAT
= 1.031E-7*(V
BAT
) + 1.036E-7A
(EQ. 4)
I
BATAVG
= 5.155E-8*(V
BAT2
+ V
BAT1
) + 1.036E-7A
(EQ. 5)
t
BACKUP
= C
BAT
*(V
BAT2
- V
BAT1
) / (I
BATAVG
+ I
LKG
)
(EQ. 6)
seconds
C
BAT
= 0.70*35.96 = 25.2 days
(EQ. 7)
FIGURE 13. SUPERCAPACITOR CHARGING CIRCUIT
2.7V to 5.5V
V
DD
V
BAT
GND
1N4148
C
BAT
ISL12021
23
FN6451.0
March 30, 2007
Example 2. Calculating a Capacitor Value for a
Given Backup Time
Referring to Figure 13 again, the capacitor value needs to be
calculated to give 2 months (60 days) of backup time, given
V
DD
= 5.0V. As in Example 1, the V
BAT
voltage will vary from
4.7V down to 1.8V. We will need to rearrange Equation 3 to
solve for capacitance:
Using the terms described above, this equation becomes:
where
t
BACKUP
= 60 days*86, 400s/day = 5.18 E6s
I
BATAVG
= 4.387 E-7A (same as Example 1)
I
LKG
= 0 (assumed)
V
BAT2
= 4.7V
V
BAT1
= 1.8V
Solving gives
C
BAT
= 5.18 E6 * (4.387 E-7)/(2.9) = 0.784F
If the 30% tolerance is included for tolerances, then worst
case cap value would be:
C
BAT
= 1.3 *.784 = 1.02F
C
BAT
= dT*I/dV
(EQ. 8)
C
BAT
= t
BACKUP
*(I
BATAVG
+ I
LKG
)/(V
BAT2
– V
BAT1
)
(EQ. 9)
ISL12021
24
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6451.0
March 30, 2007
ISL12021
Thin Shrink Small Outline Plastic Packages (TSSOP)
α
INDEX
AREA
E1
D
N
123
-B-
0.10(0.004) C AM BS
e
-A-
b
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
c
E
0.25(0.010) BM M
L
0.25
0.010
GAUGE
PLANE
A2
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
0.05(0.002)
M14.173
14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.047 - 1.20 -
A1 0.002 0.006 0.05 0.15 -
A2 0.031 0.041 0.80 1.05 -
b 0.0075 0.0118 0.19 0.30 9
c 0.0035 0.0079 0.09 0.20 -
D 0.195 0.199 4.95 5.05 3
E1 0.169 0.177 4.30 4.50 4
e 0.026 BSC 0.65 BSC -
E 0.246 0.256 6.25 6.50 -
L 0.0177 0.0295 0.45 0.75 6
N14 147
α
0
o
8
o
0
o
8
o
-
Rev. 2 4/06

ISL12021CVZ

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
IC RTC CLK/CALENDAR I2C 14-TSSOP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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