4
FN6451.0
March 30, 2007
I
2
C Interface Specifications Test Conditions: V
DD
= +2.7 to +5.5V, Temperature = -20°C to +70°C, unless otherwise specified.
SYMBOL PARAMETER TEST CONDITIONS MIN
TYP
(Note 7) MAX UNITS NOTES
V
IL
SDA and SCL input buffer LOW
voltage
-0.3 0.3 x V
DD
V
V
IH
SDA and SCL Input Buffer HIGH
Voltage
0.7 x V
DD
V
DD
+ 0.3 V
Hysteresis SDA and SCL Input Buffer
Hysteresis
0.05 x V
DD
V
V
OL
SDA Output Buffer LOW Voltage,
Sinking 3mA
V
DD
= 5V, I
OL
= 3mA 0.4 V
C
PIN
SDA and SCL Pin Capacitance T
A
= +25°C, f = 1MHz,
V
DD
= 5V, V
IN
= 0V,
V
OUT
= 0V
10 pF
f
SCL
SCL Frequency 400 kHz
t
IN
Pulse Width Suppression Time at
SDA and SCL Inputs
Any pulse narrower than the
max spec is suppressed.
50 ns
t
AA
SCL Falling Edge To SDA Output
Data Valid
SCL falling edge crossing 30%
of V
DD
, until SDA exits the
30% to 70% of V
DD
window.
900 ns
t
BUF
Time the Bus Must be Free Before
The Start of a New Transmission
SDA crossing 70% of V
DD
during a STOP condition, to
SDA crossing 70% of V
DD
during the following START
condition.
1300 ns
t
LOW
Clock LOW Time Measured at the 30% of V
DD
crossing.
1300 ns
t
HIGH
Clock HIGH Time Measured at the 70% of V
DD
crossing.
600 ns
t
SU:STA
START Condition Setup Time SCL rising edge to SDA falling
edge. Both crossing 70% of
V
DD
.
600 ns
t
HD:STA
START Condition Hold Time From SDA falling edge
crossing 30% of V
DD
to SCL
falling edge crossing 70% of
V
DD
.
600 ns
t
SU:DAT
Input Data Setup Time From SDA exiting the 30% to
70% of V
DD
window, to SCL
rising edge crossing 30% of
V
DD.
100 ns
t
HD:DAT
Input Data Hold Time From SCL falling edge
crossing 30% of V
DD
to SDA
entering the 30% to 70% of
V
DD
window.
0 900 ns
t
SU:STO
STOP Condition Setup Time From SCL rising edge
crossing 70% of V
DD
, to SDA
rising edge crossing 30% of
V
DD
.
600 ns
t
HD:STO
STOP Condition Hold Time From SDA rising edge to SCL
falling edge. Both crossing
70% of V
DD
.
600 ns
t
DH
Output Data Hold Time From SCL falling edge
crossing 30% of V
DD
, until
SDA enters the 30% to 70% of
V
DD
window.
0ns
ISL12021
5
FN6451.0
March 30, 2007
SDA vs SCL Timing
Symbol Table
t
R
SDA and SCL Rise Time From 30% to 70% of V
DD.
20 + 0.1 x Cb 300 ns
t
F
SDA and SCL Fall Time From 70% to 30% of V
DD.
20 + 0.1 x Cb 300 ns
Cb Capacitive loading of SDA or SCL Total on-chip and off-chip 10 400 pF
R
PU
SDA and SCL Bus Pull-up Resistor
Off-chip
Maximum is determined by t
R
and t
F
.
For Cb = 400pF, max is about
2~2.5kΩ.
For Cb = 40pF, max is about
15~20kΩ
1kΩ
NOTES:
2. Temperature Conversion is inactive below 2.7V V
BAT
3. IRQ/F
OUT
Inactive.
4. V
IL
= V
DD
x 0.1, V
IH
= V
DD
x 0.9, f
SCL
= 400kHz
5. V
DD
> V
BAT
+V
BATHYS
6. Bit BSW = 0 (Standard Mode), V
BAT
1.8V
7. Specified at +25°C.
8. In order to ensure proper timekeeping, the V
DD SR-
specification must be followed.
9. Parameter is not 100% tested.
10. These are I
2
C specific parameters and are not tested, however, they are used to set conditions for testing devices to validate specification.
I
2
C Interface Specifications Test Conditions: V
DD
= +2.7 to +5.5V, Temperature = -20°C to +70°C, unless otherwise specified.
SYMBOL PARAMETER TEST CONDITIONS MIN
TYP
(Note 7) MAX UNITS NOTES
t
SU:STO
t
DH
t
HIGH
t
SU:STA
t
HD:STA
t
HD:DAT
t
SU:DAT
SCL
SDA
(INPUT TIMING)
SDA
(OUTPUT TIMING)
t
F
t
LOW
t
BUF
t
AA
t
R
WAVEFORM INPUTS OUTPUTS
Must be steady Will be steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes Allowed
Changing:
State Not Known
N/A Center Line is
High Impedance
ISL12021
6
FN6451.0
March 30, 2007
General Description
The ISL12021 device is a low power real time clock (RTC)
with embedded temperature sensors. It contains crystal
frequency compensation circuitry over the operating
temperature range, clock/calendar, power fail and low
battery monitors, brown out indicator with separate
(LVRSET
) reset pin, 1 periodic or polled alarm, intelligent
battery backup switching and 128 Bytes of battery-backed
user SRAM.
The oscillator uses an external, low cost 32.768kHz crystal.
The real time clock tracks time with separate registers for
hours, minutes and seconds. The device has calendar
registers for date, month, year and day of the week. The
calendar is accurate through 2099, with automatic leap year
correction. In addition, the ISL12021 could be programmed
for automatic Daylight Saving Time (DST) adjustment by
entering local DST information.
The ISL12021’s alarm can be set to any clock/calendar
value for a match. For example, every minute, every
Tuesday or at 5:23 AM on March 21. The alarm status is
available by checking the Status Register, or the device can
be configured to provide a hardware interrupt via the IRQ
pin. There is a repeat mode for the alarm allowing a periodic
interrupt every minute, every hour, every day, etc.
The device also offers a backup power input pin. This V
BAT
pin allows the device to be backed up by battery or Super
Cap with automatic switchover from V
DD
to V
BAT
. The
ISL12021 device is specified for V
DD
= 2.7V to 5.5V and the
clock/calendar portion of the device remains fully operational
in battery backup mode down to 1.8V (Standby Mode). The
V
BAT
level is monitored and reported against preselected
levels. The first report is registered when the V
BAT
level falls
below 85% of nominal level, the second level is set for 75%.
Battery levels are stored in V
BATM
registers.
The ISL12021 offers a “Brown Out” alarm once the V
DD
falls
below a pre-selected trip level. This allows system CPU to
save vital information to memory before complete power
loss. There are six V
DD
levels that could be selected for
initiation of brown out alarm.
Pin Descriptions
X1, X2
The X1 and X2 pins are the input and output, respectively, of
an inverting amplifier. An external 32.768kHz quartz crystal
is used with the device to supply a timebase for the real time
clock. Internal compensation circuitry with internal
temperature sensor provides frequency corrections for
selected popular crystals to ±5ppm over the operating
temperature range from -40°C to +85°C. (See “Application
Section” on page 21 for recommended crystal). The
ISL12021 allows the user to input via I
2
C serial bus the
temperature variation profiles of crystals not listed in the
“Application Section” on page 21. This oscillator
compensation network can also be used to calibrate the
initial crystal timing accuracy at room temperature. The
device can also be driven directly from a 32.768kHz source
at pin X1.
VBAT
This input provides a backup supply voltage to the device.
VBAT supplies power to the device in the event that the VDD
supply fails. This pin can be connected to a battery, a Super
Capacitor or tied to ground if not used. See the Battery
Monitor parameter in the DC Operating Characteristics-RTC
on page 3.
IRQ (Interrupt Output)
This pin provides an interrupt signal output. This signal
notifies a host processor that an alarm has occurred and
requests action. It is an open drain active low output. Once
triggered, the output will stay low until the Alarm status
register bit is reset or, if the autoreset function is used, a
read is performed to the status register.
F
OUT
(Frequency Output)
This pin outputs a clock signal which is related to the crystal
frequency. The frequency output is user selectable and
enabled via the I
2
C bus. It is an open drain output.
Serial Clock (SCL)
The SCL input is used to clock all serial data into and out of
the device. The input buffer on this pin is always active (not
gated). It is disabled when the backup power supply on the
V
BAT
pin is activated to minimize power consumption.
FIGURE 1. STANDARD OUTPUT LOAD FOR TESTING THE
DEVICE WITH V
DD
= 5.0V
SDA,
IRQ
and FOUT
1533Ω
100pF
5.0V
FOR V
OL
= 0.4V
AND I
OL
= 3mA
EQUIVALENT AC OUTPUT LOAD CIRCUIT FOR V
DD
= 5V
FIGURE 2. RECOMMENDED CRYSTAL CONNECTION
X1
X2
ISL12021

ISL12021CVZ

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
IC RTC CLK/CALENDAR I2C 14-TSSOP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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