ISL12021CVZ Datasheet ISL12021CVZ | P16-P18

FN6451.0

March 30, 2007

GAIN FACTOR OF ATR BIT (BETA)<3:0>

Beta is specified to take care of the Cm variations of the

crystal. Most crystals specify Cm around 2.2fF. For example,

if Cm > 2.2fF, the actual ATR steps may reduce from

1ppm/step to approximately 0.80ppm/step. Beta is then used

to adjust for this variation and restore the step size to

1ppm/step.

The value for BETA should only be changed while the TSE

(Temp Sense Enable) bit is “0”. The procedure for writing the

BETA register involves two steps. First, Write the new value

of BETA with TSE = 0. Then Write the same value of BETA

with TSE = 1. This will insure the next temp sense cycle will

use the new BETA value. BETA values are limited in the

range from 0100 to 1100 as shown in Table 16

Final Analog Trimming Register (FATR)

This register shows the final setting of ATR after temperature

correction. It is read-only, the user cannot overwrite a value

to this register. This value is accessible as a means of

monitoring the temperature compensation function. See

Table 17.

Final Digital Trimming Register (FDTR)

This Register shows the final setting of DTR after

temperature correction. It is read-only, the user cannot

overwrite a value to this register. The value is accessible as

a means of monitoring the temperature compensation

function. The corresponding clock adjustment values are

shown in Table 19. The DTR setting is only positive as it is

used to correct for the negative drift of a normal crystal over

temperature.

ALARM Registers (10h to 15h)

The alarm register bytes are set up identical to the RTC

an enable bit (enable = “1”). These enable bits specify which

alarm registers (seconds, minutes, etc.) are used to make

the comparison. Note that there is no alarm byte for year.

The alarm function works as a comparison between the

alarm registers and the RTC registers. As the RTC

advances, the alarm will be triggered once a match occurs

between the alarm registers and the RTC registers. Any one

alarm register, multiple registers, or all registers can be

enabled for a match.

There are two alarm operation modes: Single Event and

periodic Interrupt Mode:

• Single Event Mode is enabled by setting the bit 7 on any

of the Alarm registers (ESCA0... EDWA0) to “1”, the IM bit

to “0”, and disabling the frequency output. This mode

permits a one-time match between the Alarm registers

and the RTC registers. Once this match occurs, the ALM

bit is set to “1” and the IRQ

output will be pulled low and

will remain low until the ALM bit is reset. This can be done

manually or by using the auto-reset feature.

• Interrupt Mode is enabled by setting the bit 7 on any of

the Alarm registers (ESCA0... EDWA0) to “1”, the IM bit to

TABLE 15. FREQUENCY OF TEMPERATURE SENSING AND

CORRECTION BIT

BTSE BTSR

TC PERIOD IN

BATTERY MODE

00OFF

01OFF

1 0 10 Minutes

1 1 1 Minute

TABLE 16. BETA VALUES

BETA<3:0> ATR STEP ADJUSTMENT

0100 0.500

0101 0.625

0110 0.750

0111 0.875

1000 1.00

1001 1.125

1010 1.250

1011 1.375

1100 1.500

TABLE 17. FINAL ANALOG TRIMMING REGISTER

ADDR 7 6 5 4 3 2 1 0

0Eh 0 0 FATR5 FATR4 FATR3 FATR2 FATR1 FATR0

TABLE 18. FINAL DIGITAL TRIMMING REGISTER

ADDR 76543 2 1 0

0Fh FDTR2 FDTR1 FDTR0

TABLE 19. CLOCK ADJUSTMENT VALUES FOR FINAL

DIGITAL TRIMMING REGISTER

DTR<2:0> DECIMAL

ppm

ADJUSTMENT

000 0 0

001 1 32

010 2 64

011 3 96

100 4 128

101 5 160

110 6 196

111 7 -32

ISL12021

FN6451.0

March 30, 2007

“1”, and disabling the frequency output. The IRQ output

will now be pulsed each time an alarm occurs. This means

that once the interrupt mode alarm is set, it will continue to

alarm for each occurring match of the alarm and present

time. This mode is convenient for hourly or daily hardware

interrupts in microcontroller applications such as security

cameras or utility meter reading.

To clear a single event alarm, the ALM bit in the status

bit is set to 1 (address 08h, bit 7), the ALM bit will

automatically be cleared when the status register is read.

Following are examples of both Single Event and periodic

Interrupt Mode alarms.

Example 1

• Alarm set with single interrupt (IM = ”0”)

• A single alarm will occur on January 1 at 11:30am.

• Set Alarm registers as follows:

After these registers are set, an alarm will be generated when

the RTC advances to exactly 11:30am on January 1 (after

seconds changes from 59 to 00) by setting the ALM bit in the

status register to “1” and also bringing the IRQ

output low.

Example 2

• Pulsed interrupt once per minute (IM = ”1”)

• Interrupts at one minute intervals when the seconds

• Set Alarm registers as follows:

Once the registers are set, the following waveform will be

seen at IRQ

Note that the status register ALM bit will be set each time the

alarm is triggered, but does not need to be read or cleared

Time Stamp V

to Battery Registers (TSV2B)

The TSV2B Register bytes are identical to the RTC register

bytes, except they do not extend beyond the Month. The Time

Stamp captures the FIRST V

to Battery Voltage transition

time, and will not update upon subsequent events, until cleared

(only the first event is captured before clearing). Set CLRTS = 1

to clear this register (Add 09h, PWR_V

Note that the time stamp registers are cleared to all “0”,

including the month and day, which is different from the RTC

and alarm registers (those registers default to 01h). This is

the indicator that no time stamping has occurred since the

last clear or initial powerup. Once a time stamp occurs, there

will be a non-zero time stamp.

Time Stamp Battery to V

Registers (TSB2V)

The Time Stamp Battery to V

to the RTC register bytes, except they do not extend beyond

Month. The Time Stamp captures the LAST transition of

BAT

to V

(only the last event of a series of power up/down

events is retained). Set CLRTS = 1 to clear this register (Add

09h, PWR_V

DST Control Registers (DSTCR)

8 bytes of control registers have been assigned for the

Daylight Savings Time (DST) functions. DST beginning time

is controlled by the registers DstMoFd, DstDwFd, DstDtFd

ALARM

BIT

DESCRIPTION76543210HEX

SCA0 00000000 00hSeconds disabled

MNA0 10110000 B0hMinutes set to 30,

enabled

HRA0 10010001 91hHours set to 11,

enabled

DTA0 10000001 81hDate set to 1,

enabled

MOA0 10000001 81hMonth set to 1,

enabled

DWA0 00000000 00hDay of week

disabled

ALARM

BIT

DESCRIPTION76543210HEX

SCA0 10110000B0hSeconds set to 30,

enabled

MNA0 0000000000hMinutes disabled

HRA0 0000000000hHours disabled

DTA0 0000000000hDate disabled

MOA0 0000000000hMonth disabled

DWA0 0000000000hDay of week disabled

ALARM

BIT

DESCRIPTION76543210HEX

60s

RTC AND ALARM REGISTERS ARE BOTH “30s”

FIGURE 5. IRQ WAVEFORM

BMODE

CLRTS

CLRTS INT+

BAT

FIGURE 6.

ISL12021

FN6451.0

March 30, 2007

and DstHrFd. DST ending time is controlled by DstMoRv,

DstDwRv, DstDtRv and DstHrRv.

The following tables describe the structure and functions of

the DSTCR.

DST FORWARD REGISTERS (20H TO 23H)

DSTE is the DST Enabling Bit located in bit 7 of register 20h

(DstMoFdxx). Set DSTE = 1 will enable the DSTE function.

Upon powering up for the first time (including battery), the

DSTE bit defaults to “0”.

The beginning of DST is controlled by the following DST

Registers.

DstMoFd sets the Month that DST starts. The default value

for the DST begin month is April (04h)

DstDw sets the Day of the Week that DST starts. DstDwFdE

sets the priority of the Day of the Week over the Date. For

DstDwFdE=1, Day of the week is the priority. Note that Day

of the week counts from 0 to 6, like the RTC registers.

The default for the DST Forward Day of the Week is Sunday

(80h).

DstDtfd control which Date DST begins. The defaulted value

for DST date is on the first date of the month. DstDtFd is only

effective if DstDwFdE = 0.

DstHrFd controls the hour that DST begins. It includes the

MIL bit which is in the corresponding RTC register. These

two registers need to match formats (Military or AM/PM) in

order for the DST function to work. The default value for DST

hour is 2:00AM. The time is advanced from 2:00:00AM to

3:00:00AM for this setting.

DST REVERSE REGISTERS (24H TO 27H)

The end of DST is controlled by the following DST Registers.

DstMoRv sets the Month that DST ends. The default value

for the DST end month is October (10h).

DstDwRv controls which count of the Day of the Week that

DST should end. DstDwRvE sets the priority of the Day of the

Week over the Date. For DstDwRvE = 1, Day of the week is

the priority. Note that Day of the week counts from 0 to 6, like

the RTC registers.

The default for DST end is Sunday (80h).

DstDtRv controls which Date DST ends. The default value

DST is set to end is the first date of the month. The DstDtRv

is only effective if the DstDwRvE = 0.

DstHrRv controls the hour that DST ends. It includes the MIL

bit which is in the corresponding RTC register. These two

registers need to match formats (Military or AM/PM) in order

for the DST function to work. The default value sets the DST

end at 2:00AM. The time is set back from 2:00:00AM to

1:00:00AM for this setting.

TABLE 20. DST FORWARD REGISTERS

Name76543210

DstMoFd DSTE Not Used Not Used DstMoFd20 DstMoFd13 DstMoFd12 DstMoFd11 DstMoFd10

DstDwFd DstDwFdE Not Used Not Used Not Used Not Used DstDwFd12 DstDwFd11 DstDwFd10

DstDtFd Not Used Not Used DstDtFd21 DstDtFd20 DstDtFd13 DstDtFd12 DstDtFd11 DstDtFd10

DstHrFd MIL Not Used DstHrFd21 DstHrFd20 DstHrFd13 DstHrFd12 DstHrFd11 DstHrFd10

TABLE 21. DST REVERSE REGISTERS

Name 76543210

DstMoRv Not Used Not Used Not Used DstMoRv20 DstMoRv13 DstMoRv12 DstMoRv11 DstMoRv10

DstDwRv DstDwRvE Not Used Not Used Not Used Not Used DstDwRv12 DstDwRv11 DstDwRv10

DstDtRv Not Used Not Used DstDtRv21 DstDtRv20 DstDtRv13 DstDtRv12 DstDtRv11 DstDtRv10

DstHrRv MIL Not Used DstHrRv21 DstHrRv20 DstHrRv13 DstHrRv12 DstHrRv11 DstHrRv10

ISL12021

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ISL12021CVZ

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IC RTC CLK/CALENDAR I2C 14-TSSOP

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