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NHS3100/A1Z

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45
NXP Semiconductors
NHS3100
Temperature logger
NHS3100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Product data sheet Rev. 6.03 — 15 June 2018
13 / 45
The SFRO runs at 8 MHz. The system clock is derived from it and can be set to 8 MHz,
4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz, or 62.5 kHz (Note: Some features
are not available when using the lower clock speeds). The TFRO runs at 32.768 kHz and
is the clock source for the timer unit. The TFRO cannot be disabled.
Following reset, the NHS3100 starts operating at the default 500 kHz system clock
frequency to minimize dynamic current consumption during the boot cycle.
The SYSAHBCLKCTRL register gates the system clock to the various peripherals and
memories. The temperature sensor receives a fixed clock frequency, irrespective of the
system clock divider settings, while the digital part uses the system clock (AHB clock 0).
aaa-015352
SYSTEM FRO
(8 MHz)
SYSTEM CLOCK
DIVIDER
SYSCLKTRIM
fixed-frequency taps
system clock (AHB clock 0)
peripheral clocks
analog peripheral clocks
SPI/SSP
WDT_PCLK
wake-up timer
PMU/always-on-domain
SYSCLKDIV[2:0]
SPI/SSP CLOCK
DIVIDER
SSPCLKDIV
WDTCLKDIV
SYSAHBCLKCTRL
TIMER FRO
(32 kHz)
TMRCLKTRIM
TMRUEN
WATCHDOG CLOCK
DIVIDER
WDTSEL
0
0
Figure 6. NHS3100 clock generator block diagram
8.3.2 Reset
Reset has three sources on the NHS3100:
• The RESETN pin
• Watchdog reset
• A software reset
NXP Semiconductors
NHS3100
Temperature logger
NHS3100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Product data sheet Rev. 6.03 — 15 June 2018
14 / 45
8.4 Power management
The Power Management Unit (PMU) controls the switching between available power
sources and the powering of the different voltage domains in the IC.
8.4.1 System power architecture
The NHS3100 accepts power from two different sources: from the external power supply
pin VDDBAT, or from the built-in NFC/RFID rectifier.
The NHS3100 has a small automatic source selector that monitors the power inputs
(VBAT and VNFC, see Figure 7) as well as pin RESETN. The PSWBAT switch is kept
open until a trigger is given on pin RESETN or via the NFC field. If the trigger is given,
the always-on domain, VDD_ALON, itself is powered via the PSWBAT or the PSWNFC
switch: via VBAT, if VBAT > 1.72 V, or VNFC. Priority is given to VBAT when both VBAT
and VNFC are present.
The automatic source selector unit in the PMU decides on the powering of the internal
domains based on the power source.
• If a voltage > 1.72 V is detected on VBAT and not VNFC, VBAT powers the internal
domains after a trigger on pin RESETN or via NFC.
• If a voltage ≤ 1.72 V is detected on VBAT, and a higher voltage is detected on VNFC,
the internal domains are powered from VNFC.
• If a voltage > 1.72 V is detected at both VBAT and VNFC, the internal domains are
powered from VBAT.
• Switchover between power sources is possible. If initially both VBAT and VNFC are
available, the system is powered from VBAT. If VBAT then becomes unavailable
(because it is switched off externally, or by a PSWBAT/PSWNFC power switch
override), the internal domains are immediately powered from VNFC. Switchover is
supported in both directions.
• The user can force the selection of the VBAT input by disabling the automatic power
switch, which disables the automatic source selector voltage comparator.
When on NFC power only (passive operation), connecting one or more 100 nF external
capacitors in parallel to a GPIO pad, and setting that pad as an output driven to logic 1, is
advised. Preferably a high-drive pin should be chosen and several pins can be connected
in parallel.
PSWNFC and PSWBAT are the power switches. PSWNFC connects power to the
VDD_ALON power net when an RF field is present. PSWBAT connects power from the
battery when a positive edge is detected on RESETN. If no RF power is available, the
PMU can open this PSWBAT switch, effectively switching off the device. After connecting
VDDBAT to a power source, the PSWBAT switch is open until a rising edge is detected
on RESETN or RF power is applied.
Each component of the NHS3100 resides in one of several internal power domains,
as indicated in Figure 7. The domains are VBAT, VNFC, VDD_ALON, VDD1V2 and
VDD1V6. The domains VDD_ALON, VDD1V2 and VDD1V6 are either powered or not
powered, depending on the mode of the NHS3100. There are 5 modes:
• Active
• Sleep
• Deep-sleep
• Deep power-down
NXP Semiconductors
NHS3100
Temperature logger
NHS3100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Product data sheet Rev. 6.03 — 15 June 2018
15 / 45
• Battery-off
The VDD_ALON domain contains BrownOut Detection (BOD). When enabled, it raises a
BOD interrupt if the VDD_ALON voltage drops below 1.8 V.
The PMU controls the Active, Sleep, Deep-sleep, and Deep power-down modes. In this
way, the power flows to the different internal components.
The PMU has two LDOs powering the internal VDD1V2 and VDD1V6 voltage domains.
LDO1V2 converts voltages in the range 1.72 V to 3.6 V to 1.22 V. LDO1V6 converts
voltages in the range 1.72 V to 3.6 V to 1.6 V. Each LDO can be enabled separately.
When powered via VNFC, a 1.2 nF buffer capacitor is included at the input of the LDOs.
The trigger detector (not shown in Figure 7) and the power gate have a leakage of less
than 50 nA, allowing a long shelf life before activation.
aaa-019962
AUTOMATIC SOURCE SELECTOR UNIT
< 1.85 V
1.72 V to 3.6 V
1.72 V to 3.6 V
1.2 V
75 kΩ
PMU
32 kHz FRO
ALWAYS-ON DOMAIN
pin mode override if PCON.WAKEUP set,
when entering Deep power-down mode
DIGITAL CORE
PERIPHERALS
VDD_ALON
PSWNFC
PSWBAT
VNFC
VBAT
RESETN
VDDBAT
LB
LA
PIO0_0
WAKEUP
ANALOG
PERIPHERALS,
FLASH MEMORY
EEPROM MEMORY
NFC core
RTC
BOD
LDO1V2
SFRO
LDO1V6
GPREGx
1.6 V
Figure 7. NHS3100 power architecture
Table 9 summarizes the PMU states and settings of the LDOs. Figure 8 shows the state
transitions.
Table 10 and Table 11 summarize the events that can influence wake-up from Deep
power-down or Deep-sleep modes (DEEPPDN or DEEPSLEEP to ACTIVE state
transition).
Table 9. IC power states
State VDD_ALON DPDN
[1]
Sleep or Deep-
sleep
LDO1 (1.2 V) LDO2 (1.6 V)
BATTERY-OFF (No power) no X
[2]
X
[2]
off off
ACTIVE yes 0 0 on on
DEEPPDN yes 1 0 off off
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45

NHS3100/A1Z

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Buy NHS3100/A1Z
Manufacturer:
NXP Semiconductors
Description:
Board Mount Temperature Sensors NHS3100 Temperature Logger
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New from this manufacturer.
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