NXP Semiconductors
NHS3100
Temperature logger
NHS3100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Product data sheet Rev. 6.03 — 15 June 2018
4 / 45
6 Block diagram
The internal block diagram of the NHS3100 is shown in Figure 1. It consists of a Power
Management Unit (PMU), clocks, timers, a digital computation, and a control cluster
(ARM Cortex-M0+ and memories) and AHB-APB slave modules.
POWER
PADS
PADS
WAKE-UP
TIMER
32 kHz FRO
CLOCK
SHOP
EXTERNAL
POWER
SWITCH
INTERNAL
POWER
SWITCHES
POR
LDO (1.6 V)
LDO (1.2 V)
8 MHz FRO
MFIO
(DIGITAL)
HIGH
DRIVE
DIGITAL
SWITCH
MATRIX
I
2
C-BUS SPI
GPIO
32 kB FLASH
4 kB EEPROM
ARM M0+
AHB-APB BRIDGE
8 kB SRAM
PMU
NFC/RFID
FLASH
CONTROL
EEPROM
CONTROL
TIMERS WATCHDOG SYSCONFIG
IOCONFIG
TEMPERATURE
SENSOR
I
2
C-BUS
aaa-015348
Figure 1. NHS3100 block diagram
NXP Semiconductors
NHS3100
Temperature logger
NHS3100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Product data sheet Rev. 6.03 — 15 June 2018
5 / 45
7 Pinning information
7.1 Pinning
7.1.1 HVQFN24 package
Figure 2 shows the pad layout of the NHS3100 in the HVQFN24 package.
aaa-015349
Transparent top view
PIO0_7/CT16B_M1
PIO0_8/MISO
PIO0_9/MOSI
PIO0_3/CT16B_M0
PIO0_6/SCLK PIO0_10/CT32B_M0/SWCLK
PIO0_2/SSEL PIO0_11/CT32B_M1/SWDIO
PIO0_1/CLKOUT (reserved)
PIO0_0/WAKEUP (reserved)
25 VSS
VDDBAT
VSS
RESETN
(reserved)
PIO0_4/SCL
PIO0_5/SDA
(
r
e
s
e
r
v
e
d
)
(
r
e
s
e
r
v
e
d
)
(
r
e
s
e
r
v
e
d
)
(
r
e
s
e
r
v
e
d
)
L
A
L
B
terminal 1
index area
6 13
5 14
4 15
3 16
2 17
1 18
7
8
9
10
11
12
2
4
2
3
2
2
2
1
2
0
1
9
Figure 2. Pad configuration HVQFN24
Table 3. Pad allocation table of the HVQFN24 package
Pad Symbol Pad Symbol
1 PIO0_0/WAKEUP 13
[1]
PIO0_7/CT16B_M1
2 PIO0_1/CLKOUT 14
[1]
PIO0_3/CT16B_M0
3 PIO0_2/SSEL 15
[1]
PIO0_10/CT32B_M0/SWCLK
4 PIO0_6/SCLK 16
[1]
PIO0_11/CT32B_M1/SWDIO
5 PIO0_8/MISO 17
[2]
(reserved)
6 PIO0_9/MOSI 18
[2]
(reserved)
7 VDDBAT 19 LB
8 VSS 20 LA
9 RESETN 21
[2]
(reserved)
10 (reserved) 22
[2]
(reserved)
11 PIO0_4/SCL 23
[2]
(reserved)
12 PIO0_5/SDA 24
[2]
(reserved)
[1] High source current pads. See Section 8.6.3.
[2] These pads must be tied to ground.
NXP Semiconductors
NHS3100
Temperature logger
NHS3100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Product data sheet Rev. 6.03 — 15 June 2018
6 / 45
Table 4. Pad description of the HVQFN24 package
Pad Symbol Type Description
Supply
7 VDDBAT supply positive supply voltage
8 VSS supply ground
GPIO
[1]
PIO0_0 I/O GPIO1
WAKEUP I Deep power-down mode wake-up pin
[2]
PIO0_1 I/O GPIO2
CLKOUT O clock output
PIO0_2 I/O GPIO3
SSEL I SPI/SSP serial select line
PIO0_3 I/O GPIO14
CT16B_M0 O 16-bit timer match output 0
PIO0_4 I/O GPIO11
SCL I/O I
2
C-bus SCL clock line
PIO0_5 I/O GPIO12
SDA I/O I
2
C-bus SDA data line
PIO0_6 I/O GPIO4
SCLK I/O SPI/SSP serial clock line
PIO0_7 I/O GPIO13
CT16B_M1 O 16-bit timer match output 1
PIO0_8 I/O GPIO5
MISO O SPI/SSP master-in slave-out line
PIO0_9 I/O GPIO6
MOSI I SPI/SSP master-out slave-in line
PIO0_10 I/O GPIO
CT32B_M0 O 32-bit timer match output 0
15
SWCLK I ARM SWD clock
PIO0_11 I/O GPIO
CT32B_M1 O 32-bit timer match output 1
16
SWDIO I/O ARM SWD I/O
Radio
20 LA A NFC antenna/coil terminal A
19 LB A NFC antenna/coil terminal B
Reset
9 RESETN I external reset input
[3]
[1] The GPIO port is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 0 pads
depends on the function selected through the IOCONFIG register block.

NHS3100/A1Z

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Board Mount Temperature Sensors NHS3100 Temperature Logger
Lifecycle:
New from this manufacturer.
Delivery:
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