NXP Semiconductors
NHS3100
Temperature logger
NHS3100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Product data sheet Rev. 6.03 — 15 June 2018
35 / 45
11 Dynamic characteristics
11.1 I/O pins
Table 21. I/O dynamic characteristics
These characteristics apply to standard port pins and RESETN pin.
T
amb
= −40 °C to +85 °C.
Symbol Parameter Conditions Min Typ Max Unit
t
r
rise time pin configured as output 3.0 - 5.0 ns
t
f
fall time pin configured as output 2.5 - 5.0 ns
11.2 I
2
C-bus
Table 22. I
2
C-bus dynamic characteristics
See UM10204 - I
2
C-bus specification and user manual (Ref. 3) for details. T
amb
= −40 °C to +85 °C
[1]
; see the timing
diagram in Figure 13.
Symbol Parameter Conditions Min Typ Max Unit
Standard-mode 0 - 100 kHzf
SCL
SCL clock frequency
Fast-mode 0 - 400 kHz
Standard-mode
[2]
[3]
[4]
- - 300 nst
f
fall time of both SDA and SCL
signals
Fast-mode
[2]
[3]
[4]
20 + 0.1 × C
b
- 300 ns
Standard-mode 4.7 - - µst
LOW
LOW period of the SCL clock
Fast-mode 1.3 - - µs
Standard-mode 4.0 - - µst
HIGH
HIGH period of the SCL clock
Fast-mode 0.6 - - µs
Standard-mode
[2]
[5]
[6]
0 - - µst
HD;DAT
data hold time
Fast-mode
[2]
[5]
[6]
0 - - µs
Standard-mode
[7]
[8]
250 - - nst
SU;DAT
data setup time
Fast-mode
[7]
[8]
100 - - ns
[1] Parameters are valid over operating temperature range unless otherwise specified.
[2] A device must internally provide a hold time of at least 300 ns for the SDA signal (regarding the V
IH(min)
of the SCL signal). The hold time is to bridge the
undefined region of the falling edge of SCL.
[3] C
b
= total capacitance of one bus line in pF.
[4] The maximum t
f
for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage t
f
is specified at 250 ns. It allows
series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified t
f
.
[5] t
HD;DAT
is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge.
[6] The maximum t
HD;DAT
could be 3.45 μs and 0.9 μs for Standard-mode and Fast-mode. However, it must be less than the maximum of t
VD;DAT
or t
VD;ACK
by a transition time (see Ref. 3). Only meet this maximum if the device does not stretch the LOW period (t
LOW
) of the SCL signal. If the clock stretches the
SCL, the data must be valid by the setup time before it releases the clock.
[7] t
SU;DAT
is the data setup time that is measured against the rising edge of SCL; applies to data in transmission and the acknowledge.
[8] A Fast-mode I
2
C-bus device can be used in a Standard-mode I
2
C-bus system but it must meet the requirement t
SU;DAT
= 250 ns. This requirement
is automatically the case if the device does not stretch the LOW period of the SCL signal. If it does, it must output the next data bit to the SDA line
t
r(max)
+ t
SU;DAT
= 1000 + 250 = 1250 ns before the SCL line is released. This procedure is in accordance with the Standard-mode I
2
C-bus specification.
Also, the acknowledge timing must meet this setup time.
