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NHS3100/A1Z

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45
NXP Semiconductors
NHS3100
Temperature logger
NHS3100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Product data sheet Rev. 6.03 — 15 June 2018
25 / 45
8.11 16-bit timer
8.11.1 Features
One 16-bit timer with a programmable 16-bit prescaler.
• Timer operation
• Four 16-bit match registers that allow:
– Continuous operation with optional interrupt generation on match
– Stop timer on match with optional interrupt generation
– Reset timer on match with optional interrupt generation
• Up to two CT16B external outputs corresponding to the match registers with the
following capabilities:
– Set LOW on match
– Set HIGH on match
– Toggle on match
– Do nothing on match
• Up to two match registers can be configured as Pulse Width Modulation (PWM)
allowing the use of up to two match outputs as single edge controlled PWM outputs
8.11.2 General description
The peripheral clock (PCLK), which is derived from the system clock, clocks the timer.
The timer can optionally generate interrupts or perform other actions at specified timer
values based on four match registers. The peripheral clock is provided by the system
clock.
Each timer also includes one capture input to trap the timer value when an input signal
transitions, optionally generating an interrupt.
In PWM mode, four match registers can be used to provide a single-edge controlled
PWM output on the match output pins. The use of the match registers that are not pinned
out to control the PWM cycle length is recommended.
NXP Semiconductors
NHS3100
Temperature logger
NHS3100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Product data sheet Rev. 6.03 — 15 June 2018
26 / 45
8.12 32-bit timer
8.12.1 Features
One 32-bit timer with a programmable 32-bit prescaler.
• Timer operation
• Four 32-bit match registers that allow:
– Continuous operation with optional interrupt generation on match
– Stop timer on match with optional interrupt generation
– Reset timer on match with optional interrupt generation
• Up to two CT32B external outputs corresponding to the match registers with the
following capabilities:
– Set LOW on match
– Set HIGH on match
– Toggle on match
– Do nothing on match
• Up to two match registers can be configured as PWM allowing the use of up to two
match outputs as single edge controlled PWM outputs
8.12.2 General description
The peripheral clock (PCLK), which is derived from the system clock, clocks the timer.
The timer can optionally generate interrupts or perform other actions at specified timer
values based on four match registers. The peripheral clock is provided by the system
clock.
Each timer also includes one capture input to trap the timer value when an input signal
transitions, optionally generating an interrupt.
In PWM mode, four match registers can be used to provide a single-edge controlled
PWM output on the match output pins. Use of the match registers that are not pinned out
to control the PWM cycle length is recommended.
NXP Semiconductors
NHS3100
Temperature logger
NHS3100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Product data sheet Rev. 6.03 — 15 June 2018
27 / 45
8.13 WatchDog Timer (WDT)
If the microcontroller enters an erroneous state, the purpose of the WatchDog Timer
(WDT) is to reset it within a reasonable amount of time.
When enabled, if the user program fails to feed (or reload) the WDT within a
predetermined amount of time, the WDT generates a system reset.
8.13.1 Features
• If not periodically reloaded, it internally resets the microcontroller
• Debug mode
• Enabled by software but requires a hardware reset or a WDT reset/interrupt to be
disabled
• If enabled, incorrect/incomplete feed sequence causes reset/interrupt
• Flag to indicate WDT reset
• Programmable 24-bit timer with internal prescaler
• Selectable time period from (TWDCLK × 256 × 4) to (TWDCLK × 2
24
× 4) in multiples
of TWDCLK × 4
• The WDT clock (WDCLK) source is a 2 MHz clock derived from the SFRO, or the
external clock as set by the SYSCLKCTRL register
8.13.2 General description
The WDT consists of a divide by 4 fixed prescaler and a 24-bit counter. The clock is fed
to the timer via a prescaler. The timer decrements when clocked. The minimum value by
which the counter is decremented is 0xFF. Setting a value lower than 0xFF causes 0xFF
to be loaded in the counter. Hence the minimum WDT interval is (TWDCLK × 256 × 4)
and the maximum is (TWDCLK × 2
24
× 4), in multiples of (TWDCLK × 4).
8.14 System tick timer
8.14.1 Features
• Simple 24-bit timer
• Uses dedicated exception vector
• Clocked internally by the system clock or the system clock divided by two
8.14.2 General description
The SYSTICK timer is a part of the Cortex-M0+. The SYSTICK timer can be used to
generate a fixed periodic interrupt for use by an operating system or other system.
Since the SYSTICK timer is a part of the Cortex-M0+, it facilitates porting of software by
providing a standard timer available on Cortex-M0+ based devices. The SYSTICK timer
can be used for management software.
Refer to the Cortex-M0+ Devices - Generic User Guide (Ref. 2) for details.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45

NHS3100/A1Z

Mfr. #:
Buy NHS3100/A1Z
Manufacturer:
NXP Semiconductors
Description:
Board Mount Temperature Sensors NHS3100 Temperature Logger
Lifecycle:
New from this manufacturer.
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