NXP Semiconductors
NHS3100
Temperature logger
NHS3100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Product data sheet Rev. 6.03 — 15 June 2018
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Table 11. State transition events for DEEPPDN to ACTIVE
Event Description
RESETN reset asserted
RTC event if the timer reaches preset value
WAKEUP signal on WAKEUP pin (when enabled)
RF field RF field is detected, potential NFC command input (if set in PMU)
aaa-016479
VDD_ALON
start TFRO enable 1.2 V LDO
enable 1.6 V LDO
for analog domain
and flash memory
POR always-on
domain
SFRO starts running
power
flash and
digital
power
analog
on
off
SFRO stable (64 µs)
system_por
Figure 9. NHS3100 power-up sequence
8.4.2 Power Management Unit (PMU)
The Power Management Unit (PMU) partly resides in the digital power domain and partly
in the always-on domain. The PMU controls the Sleep, Deep-sleep, and Deep power-
down modes and the power flow to the different internal circuit blocks. Five general-
purpose registers in the PMU can be used to retain data during Deep power-down mode.
These registers are located in the always-on domain. When configured, the PMU also
raises a BOD interrupt if VDD_ALON drops to below 1.8 V.
The power to the different APB analog slaves is controlled through a power-down
configuration register.
The power control register selects whether an ARM Cortex-M0+ controlled Power-down
mode (Sleep mode or Deep-sleep mode) or the Deep power-down mode is entered. It
also provides the flags for Sleep or Deep-sleep modes and Deep power-down mode
respectively. In addition, it contains the overrides for the power source selection.
8.5 Nested Vectored Interrupt Controller (NVIC)
The Nested Vectored Interrupt Controller (NVIC) is a part of the ARM Cortex-M0+. The
tight integration of the processor core and NVIC enables fast processing of interrupts,
dramatically reducing the interrupt latency.
8.5.1 Features
• NVIC that is a part of the ARM Cortex-M0+
• Tightly coupled interrupt controller provides low interrupt latency
• Controls system exceptions and peripheral interrupts
