NXP Semiconductors
NHS3100
Temperature logger
NHS3100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Product data sheet Rev. 6.03 — 15 June 2018
7 / 45
[2] If external wake-up is enabled on this pad, it must be pulled HIGH before entering Deep power-down mode and pulled
LOW for a minimum of 100 µs to exit Deep power-down mode. It has weak pull-up to VBAT or internal NFC voltage
(whichever is highest).
[3] A LOW on this pad resets the device. This reset causes I/O ports and peripherals to take on their default states, and
processor execution to begin at address 0. It has weak pull-up to V
DDBAT
.
7.1.2 WLCSP25 package
Figure 3 shows the ball layout of the NHS3100 in the WLCSP25 package.
A
B
C
D
E
ball A1
index area
NHS3100UK
aaa-024187
Transparent top view
1 2 3 4 5
Figure 3. Ball configuration WLCSP25
Table 5. Ball allocation table of the WLCSP25 package
Ball Symbol Ball Symbol
A1 VDDBAT C4
[1]
PIO0_7/CT16B_M1
A2 VSS C5
[1]
PIO0_11/CT32B_M1/SWDIO
A3 RESETN D1 PIO0_0/WAKEUP
A4 PIO0_4/SCL D2 PIO0_1/CLKOUT
A5 PIO0_5/SDA D3
[2]
(reserved)
B1 PIO0_8/MISO D4
[2]
(reserved)
B2 PIO0_9/MOSI D5
[2]
(reserved)
B3 (reserved) E1
[2]
(reserved)
B4
[1]
PIO0_3/CT16B_M0 E2
[2]
(reserved)
B5
[1]
PIO0_10/CT32B_M0/SWCLK E3
[2]
(reserved)
C1 PIO0_2/SSEL E4 LA
C2 PIO0_6/SCLK E5 LB
C3 VSS - -
[1] High source current balls. See Section 8.6.3.
[2] These balls must be tied to ground.
NXP Semiconductors
NHS3100
Temperature logger
NHS3100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Product data sheet Rev. 6.03 — 15 June 2018
8 / 45
Table 6. Ball description of the WLCSP25 package
Ball Symbol Type Description
Supply
A1 VDDBAT supply positive supply voltage
A2, C3 VSS supply ground
GPIO
[1]
PIO0_0 I/O GPIOD1
WAKEUP I Deep power-down mode wake-up pin
[2]
PIO0_1 I/O GPIOD2
CLKOUT O clock output
PIO0_2 I/O GPIOC1
SSEL I SPI/SSP serial select line
PIO0_3 I/O GPIOB4
CT16B_M0 O 16-bit timer match output 0
PIO0_4 I/O GPIOA4
SCL I/O I
2
C-bus SCL clock line
PIO0_5 I/O GPIOA5
SDA I/O I
2
C-bus SDA data line
PIO0_6 I/O GPIOC2
SCLK I/O SPI/SSP serial clock line
PIO0_7 I/O GPIOC4
CT16B_M1 O 16-bit timer match output 1
PIO0_8 I/O GPIOB1
MISO O SPI/SSP master-in slave-out line
PIO0_9 I/O GPIOB2
MOSI I SPI/SSP master-out slave-in line
PIO0_10 I/O GPIO
CT32B_M0 O 32-bit timer match output 0
B5
SWCLK I ARM SWD clock
PIO0_11 I/O GPIO
CT32B_M1 O 32-bit timer match output 1
C5
SWDIO I/O ARM SWD I/O
Radio
E4 LA A NFC antenna/coil terminal A
E5 LB A NFC antenna/coil terminal B
Reset
A3 RESETN I external reset input
[3]
[1] The GPIO port is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 0 pins
depend on the function selected through the IOCONFIG register block.
NXP Semiconductors
NHS3100
Temperature logger
NHS3100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2018. All rights reserved.
Product data sheet Rev. 6.03 — 15 June 2018
9 / 45
[2] If external wake-up is enabled on this pin, it must be pulled HIGH before entering Deep power-down mode and pulled
LOW for a minimum of 100 μs to exit Deep power-down mode.
[3] A LOW on this pin resets the device. This reset causes I/O ports and peripherals to take on their default states, and
processor execution to begin at address 0. It has weak pull-up to V
DDBAT
or internal NFC voltage (whichever is highest).
7.1.3 NHS3100W8 gold bump version
Figure 4 shows the bump layout of the NHS3100W8.
aaa-025706
5
4
789
1
12
11
10
32
6
pin numbering
Figure 4. Bump configuration Bump die: Top view, bumps up

NHS3100/A1Z

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Board Mount Temperature Sensors NHS3100 Temperature Logger
Lifecycle:
New from this manufacturer.
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