SST49LF080A-33-4C-NHE Datasheet SST49LF080A-33-4C-NHE-T, SST49LF080A-33-4C-NHE, SST49LF080A-33-4C-WHE | P1-P3

Data Sheet

www.microchip.com

Features

• LPC Interface Flash

– SST49LF080A: 1024K x8 (8 Mbit)

• Conforms to Intel LPC Interface Specification 1.0

• Flexible Erase Capability

– Uniform 4 KByte Sectors

– Uniform 64 KByte overlay blocks

– 64 KByte Top Boot Block protection

– Chip-Erase for PP Mode Only

• Single 3.0-3.6V Read and Write Operations

• Superior Reliability

– Endurance: 100,000 Cycles (typical)

– Greater than 100 years Data Retention

• Low Power Consumption

– Active Read Current: 6 mA (typical)

– Standby Current: 10 µA (typical)

• Fast Sector-Erase/Byte-Program Operation

– Sector-Erase Time: 18 ms (typical)

– Block-Erase Time: 18 ms (typical)

– Chip-Erase Time: 70 ms (typical)

– Byte-Program Time: 14 µs (typical)

– Chip Rewrite Time: 16 seconds (typical)

– Single-pulse Program or Erase

– Internal timing generation

• Two Operational Modes

– Low Pin Count (LPC) Interface mode for

in-system operation

– P arallel Programming (PP) Mode for fast production pro-

gramming

• LPC Interface Mode

– 5-signal communication interface supporting byte Read

and Write

– 33 MHz clock frequency operation

– WP# and TBL# pins provide hardware write protect for

entire chip and/or top boot bloc k

– Standard SDP Command Set

– Data# Polling and Toggle Bit for End-of-Write detection

– 5 GPI pins for system design flexibility

– 4 ID pins for multi-chip selection

• Parallel Programming (PP) Mode

– 11-pin multiplexed address and 8-pin data

I/O interface

– Supports fast programming In-System on

programmer equipment

• CMOS and PCI I/O Compatibility

• Packages Available

– 32-lead PLCC

– 32-lead TSOP (8mm x 14mm)

• All non-Pb (lead-free) devices are RoHS compliant

8 Mbit LPC Flash

SST49LF080A

The SST49LF080A flash memory device is designed to interface with the LPC

bus for PC and Internet Appliance application in compliance with Intel Low Pin

Count (LPC) Interface Specification 1.0. Two interface modes are supported: LPC

mode for in-system operations and Parallel Programming (PP) mode to interface

with programming equipment. The SST49LF080A flash memory device is manu-

factured with proprietary, high-performance SuperFlash® Technology. The split-

gate cell design and thick-oxide tunneling injector attain better reliability and man-

ufacturability compared with alternate approaches

8 Mbit LPC Flash

SST49LF080A

Data Sheet

Product Description

SST49LF080A flash memory device is designed to interface with the LPC bus for PC and Internet

Appliance application in compliance with Intel Low Pin Count (LPC) Interface Specification 1.0. Two

interface modes are supported: LPC mode for in-system operations and Parallel Programming (PP)

mode to interface with programming equipment.

SST49LF080A flash memory device is manufactured with proprietary, high-performance SuperFlash

Technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and

manufacturability compared with alternate approaches. The SST49LF080A device significantly

improves performance and reliability, while lowering power consumption. The SST49LF080A device

writes (Program or Erase) with a single 3.0-3.6V power supply. It uses less energy during Erase and

Program than alternative flash memory technologies. The total energy consumed is a function of the

applied voltage, current and time of application. For any give voltage range, the SuperFlash technology

uses less current to program and has a shorter erase time; the total energy consumed during any

Erase or Program operation is less than alternative flash memory technologies. The SST49LF080A

product provides a maximum Byte-Program time of 20 µsec. The entire memory can be erased and

programmed byte-by-byte typically in 16 seconds when using status detection features such as Toggle

Bit or Data# Polling to indicate the completion of Program operation. The SuperFlash technology pro-

vides fixed Erase and Program time, independent of the number of Erase/Program cycles that have

performed. Therefore the system software or hardware does not have to be calibrated or correlated to

the cumulative number of Erase cycles as is necessary with alternative flash memory technologies,

whose Erase and Program time increase with accumulated Erase/Program cycles.

To meet high density, surface mount requirements, the SST49LF080A device is offered in 32-lead

TSOP and 32-lead PLCC packages. See Figures 2 and 3 for pin assignments and Table 1 for pin

descriptions.

8 Mbit LPC Flash

SST49LF080A

Data Sheet

Functional Block Diagram

Figure 1: Functional Block Diagram

1235 B1.0

Y-Decoder

I/O Buffers and Data Latches

Address Buffers Latches

X-Decoder

SuperFlash

Memory

Control Logic

LCLK

RST# CE#MODE

GPI[4:0]

Programmer

Interface

WP#

TBL#

INIT#

ID[3:0]

LFRAME#

R/C#

OE#

WE#

A[10:0]

DQ[7:0]

LAD[3:0]

LPC

Interface

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P50

SST49LF080A-33-4C-NHE

Mfr. #:

Buy SST49LF080A-33-4C-NHE

Manufacturer:

Microchip Technology

Description:

NOR Flash 1M X 8 33MHz

Lifecycle:

New from this manufacturer.

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SST49LF080A-33-4C-NHE

SST49LF080A-33-4C-NHE

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