©2014 Silicon Storage Technology, Inc. DS20005086B 11/14
5
8 Mbit LPC Flash
SST49LF080A
Data Sheet
Table 1: Pin Description
Symbol Pin Name Type
1
Interface
FunctionsPP LPC
A
10
-A
0
Address I X Inputs f or low-order addresses during Read and Write operations.
Addresses are internally latched during a Write cycle. For the pro-
gramming interface , these addresses are latched by R/C# and share
the same pins as the high-order address inputs.
DQ
7
-DQ
0
Data I/O X To output data during Read cycles and receive input data during
Write cycles. Data is internally latched during a Write cycle. The out-
puts are in tri-state when OE# is high.
OE# Output Enable I X To gate the data output buff ers.
WE# Write Enable I X To control the Write operations.
MODE Interface
Mode Select
I X X This pin determines which interf ace is operational. When held high,
programmer mode is enab led and when held lo w, LPC mode is
enabled. This pin must be setup at pow er-up or bef ore return from
reset and not change during device operation. This pin must be held
high (V
IH
) for PP mode and low (V
IL
) for LPC mode.
INIT# Initialize I X This is the second reset pin for in-system use. This pin is inter-
nally combined with the RST# pin; If this pin or RST# pin is driven
low, identical operation is exhibited.
ID[3:0] Identification
Inputs
I X These four pins are part of the mechanism that allows multiple parts to
be attached to the same b us. The strapping of these pins is used to
identify the component.The boot de vice must have ID[3:0]=0000 for all
subsequent de vices should use sequential up-count strapping. These
pins are internally pulled-down with a resistor between 20-100 K
GPI[4:0] General
Purpose
Inputs
I X These individual inputs can be used for additional board flexibility. The
state of these pins can be read through LPC registers. These inputs
should be at their desired state before the start of the PCI clock cycle dur-
ing which the read is attempted, and should remain in place until the end
of the Read cycle. Unused GPI pins must not be floated.
TBL# Top Block
Lock
I X When low, pre v ents programming to the boot block sectors at top of
memory. When TBL# is high it disables hardware write protection for
the top block sectors. This pin cannot be left unconnected.
LAD[3:0] Address and
Data
I/O X To provide LPC control signals, as well as addresses and Command
Inputs/Outputs data.
LCLK Clock I X To provide a clock input to the control unit
LFRAME#
Frame I X To indicate start of a data transfer operation; also used to abort
an LPC cycle in progress.
RST# Reset I X X To reset the operation of the device
WP# Write Protect I X When low, prev ents programming to all but the highest addressable
bloc ks . When WP# is high it disables hardware write protection f or
these blocks . This pin cannot be left unconnected.
R/C# Row/Column
Select
IX
Select f or the Programming interf ace, this pin determines whether the address
pins are pointing to the row addresses, or to the column addresses.
RES Reserved X These pins must be left unconnected.
V
DD
P ow er Supply PWR X X T o provide power supply (3.0-3.6V)
V
SS
Ground PWR X X Circuit ground (0V reference)
CE# Chip Enable I X This signal must be asserted to select the device . When CE# is low,
the device is enabled. When CE# is high, the device is placed in low
power standby mode.
NC No Connection I X X Unconnected pins.
T1.0 25026
1. I=Input, O=Output
