©2014 Silicon Storage Technology, Inc. DS20005086B 11/14
25
8 Mbit LPC Flash
SST49LF080A
Data Sheet
Figure 11: Block-Erase Command Sequence (LPC Mode)
1235 F10.0
LFRAME#
LAD[3:0]
0000b 011Xb A[23:20] A[19:16] 0101b 0101b 0101b 1010b0101b 1010b Tri-State
TA R
Load Address YYYY 5555H in 8 Clocks
Write the 1st command to the device in LPC mode.
Address
1
1 Clock 1 Clock
1st Start
Memory
Write
Cycle
TA R
SyncData
Start next
Command
1 Clock
1 Clock2 ClocksLoad Data AAH in 2 Clocks
1111b 0000b
LCLK
LFRAME#
LAD[3:0]
0000b 011Xb
A[23:20]
A[19:16] 1010b 1010b 1010b 0101b0010b 0101b Tri-State
TA R
Load Address YYYY 2AAAH in 8 Clocks
Write the 2nd command to the device in LPC mode.
Address
1
1 Clock 1 Clock
2nd Start
Memory
Write
Cycle
TA R
SyncData
Start next
Command
1 Clock
1 Clock2 ClocksLoad Data 55H in 2 Clocks
1111b 0000b
LCLK
LFRAME#
LAD[3:0]
0000b 011Xb A[23:20] A[19:16] 0101b 0101b 0101b 1000b0101b 0000b Tri-State
TA R
Load Address YYYY 5555H in 8 Clocks
Write the 3rd command to the device in LPC mode.
Address
1
1 Clock 1 Clock
3rd Start
Memory
Write
Cycle
TA R
SyncData
Start next
Command
1 Clock
1 Clock2 ClocksLoad Data 80H in 2 Clocks
1111b 0000b
LCLK
LFRAME#
LAD[3:0]
0000b 011Xb A[23:20] A[19:16] 0101b 0101b 0101b 1010b0101b 1010b Tri-State
TA R
Load Address YYYY 5555H in 8 Clocks
Write the 4th command to the device in LPC mode.
Address
1
1 Clock 1 Clock
4th Start
Memory
Write
Cycle
TA R
SyncData
Start next
Command
1 Clock
1 Clock2 ClocksLoad Data AAH in 2 Clocks
1111b 0000b
LCLK
LFRAME#
LAD[3:0]
0000b 011Xb
A[23:20] A[19:16] 1010b 1010b 1010b 0101b0010b 0101b
A[19:16] XXXXb XXXXb XXXXb 0101b
BA
X
0000b
Tri-State
TA R
Load Address YYYY 2AAAH in 8 Clocks
Load Block Address in 8 Clocks
Write the 5th command to the device in LPC mode.
Address
1
1 Clock 1 Clock
5th
Memory
Write
Cycle
TA R
SyncData
Start next
Command
1 Clock
1 Clock2 ClocksLoad Data 55H in 2 Clocks
Load Data “50” in 2 Clocks
1111b 0000b
LCLK
LFRAME#
LAD[3:0]
0000b 011Xb A[23:20] Tri-State
TA R
Write the 6th command (target sector to be erased) to the device in LPC mode.
BA
X
= Block Address
Address
1
1 Clock 1 Clock
6th Start
Memory
Write
Cycle
TA R
SyncData
Internal
erase start
Internal
erase start
1 Clock2 Clocks
1111b 0000b
CE#
CE#
CE#
CE#
CE#
LCLK
CE#
A[31:28] A[27:24]
A[31:28] A[27:24]
A[31:28] A[27:24]
A[31:28] A[27:24]
A[31:28] A[27:24]
A[31:28] A[27:24]
Note: 1. Address must be within memory address range specified in Table 4.
©2014 Silicon Storage Technology, Inc. DS20005086B 11/14
26
8 Mbit LPC Flash
SST49LF080A
Data Sheet
Figure 12: Register Readout Command Sequence (LPC Mode)DS20005086
0000b 010Xb 1111b Tri-State
TA R
Load Address in 8 Clocks
Address
1
1 Clock 1 Clock
Start
Memory
Read
Cycle
TA R
Sync Data
Start next
1 Clock
Data out 2 Clocks1 Clock2 Clocks
0000b D[3:0] D[7:4]
0000b
1235 F11.0
LFRAME#
LAD[3:0]
LCLK
CE#
A[23:20] A[19:16] A[11:8] A[7:4] A[3:0]A[15:12]A[31:28] A[27:24]
Note: 1. See Table 9 for register addresses.
©2014 Silicon Storage Technology, Inc. DS20005086B 11/14
27
8 Mbit LPC Flash
SST49LF080A
Data Sheet
Electrical Specifications
The AC and DC specifications for the LPC interface signals (LA0[3:0], LFRAME, LCLCK and RST#) as
defined in Section 4.2.2.4 of the PCI local Bus specification, Rev. 2.1. Refer to Table 14 for the DC volt-
age and current specifications. Refer to Tables 18 through 21 and Tables 23 through 25 for the AC tim-
ing specifications for Clock, Read, Write, and Reset operations.
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute
Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these conditions or conditions greater than those defined in the
operational sections of this datasheet is not implied. Exposure to absolute maximum stress rating con-
ditions may affect device reliability.)
Temperature Under Bias .............................................. -55°C to +125°C
Storage Temperature ................................................. -65°C to +150°C
D.C. Voltage on Any Pin to Ground Potential ..............................-0.5V to V
DD
+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential ...................-2.0V to V
DD
+2.0V
Package Power Dissipation Capability (Ta=25°C) .................................... 1.0W
Surface Mount Solder Reflow Temperature
1
........................... 260°C for 10 seconds
1. Excluding certain with-Pb 32-PLCC units, all packages are 260°C capable in both non-Pb and with-Pb solder versions.
Certain with-Pb 32-PLCC package types are capable of 240°C for 10 seconds; please consult the factory for the latest
information.
Output Short Circuit Current
2
................................................... 50mA
2. Outputs shorted for no more than one second. No more than one output shorted at a time.
Table 12: Operating Range
Range Ambient Temp V
DD
Commercial 0°C to +85°C 3.0-3.6V
T12.1 25026
Table 13: AC Conditions of Test
1
1. See Figures 28 and 29
Input Rise/Fall Time Output Load
3ns C
L
=30pF
T13.1 25026

SST49LF080A-33-4C-NHE

Mfr. #:
Manufacturer:
Microchip Technology
Description:
NOR Flash 1M X 8 33MHz
Lifecycle:
New from this manufacturer.
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