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SST49LF080A-33-4C-NHE

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P50
©2014 Silicon Storage Technology, Inc. DS20005086B 11/14
28
8 Mbit LPC Flash
SST49LF080A
Data Sheet
DC Characteristics
Table 14: DC Operating Characteristics (All Interfaces)
Symbol Parameter
Limits
Test ConditionsMin Max Units
I
DD
1
1. I
DD
active while a Read or Write (Program or Erase) operation is in progress.
Active V
DD
Current LCLK (LPC mode) and Address Input (PP
mode)=V
ILT
/V
IHT
at f=33 MHz (LPC mode) or 1/
TRC min
(PP Mode)
All other inputs=V
IL
or V
IH
Read 12 mA All outputs = open, V
DD
=V
DD
Max
Write 24 mA See Note
2
2. For PP Mode: OE# = WE# = V
IH;
For LPC Mode:f=1/T
RC
min, LFRAME# = V
IH,
CE# = V
IL.
I
SB
Standby V
DD
Current
(LPC Interface)
100 µA LCLK (LPC mode) and Address Input (PP
mode)=V
ILT
/V
IHT
at f=33 MHz (LPC mode) or 1/
TRC min
(PP Mode)
LFRAME#=0.9 V
DD
, f=33 MHz, CE#=0.9 V
DD
,
V
DD
=V
DD
Max, All other inputs 0.9 V
DD
or 0.1
V
DD
I
RY
3
3. The device is in Ready mode when no activity is on the LPC bus.
Ready Mode V
DD
Cur-
rent
(LPC Interface)
10 mA LCLK (LPC mode) and Address Input (PP
mode)=V
ILT
/V
IHT
at f=33 MHz (LPC mode) or 1/
TRC min
(PP Mode)
LFRAME#=V
IL
, f=33 MHz, V
DD
=V
DD
Max
All other inputs 0.9 V
DD
or 0.1 V
DD
I
I
Input Current for Mode
and ID[3:0] pins
200 µA V
IN
=GND to V
DD
,V
DD
=V
DD
Max
I
LI
Input Leakage Current 1 µA V
IN
=GND to V
DD
,V
DD
=V
DD
Max
I
LO
Output Leakage Cur-
rent
1µAV
OUT
=GND to V
DD
,V
DD
=V
DD
Max
V
IHI
INIT# Input High Volt-
age
1.1 V
DD
+0.
5
VV
DD
=V
DD
Max
V
ILI
INIT# Input Low Volt-
age
-0.5 0.4 V V
DD
=V
DD
Min
V
IL
Input Low Voltage -0.5 0.3 V
DD
VV
DD
=V
DD
Min
V
IH
Input High Voltage 0.5
V
DD
V
DD
+0.
5
VV
DD
=V
DD
Max
V
OL
Output Low Voltage 0.1 V
DD
VI
OL
=1500 µA, V
DD
=V
DD
Min
V
OH
Output High Voltage 0.9
V
DD
VI
OH
=-500 µA, V
DD
=V
DD
Min
T14.0 25026
Table 15: Recommended System Power-up Timings
Symbol Parameter Minimum Units
T
PU-READ
1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this
parameter
Power-up to Read Operation 100 µs
T
PU-WRITE
1
Power-up to Write Operation 100 µs
T15.0 25026
©2014 Silicon Storage Technology, Inc. DS20005086B 11/14
29
8 Mbit LPC Flash
SST49LF080A
Data Sheet
Figure 13: LCLK Waveform (LPC Mode)
Table 16: Pin Capacitance
(V
DD
=3.3V, Ta=25 °C, f=1 Mhz, other pins open)
Parameter Description Test Condition Maximum
C
I/O
1
I/O Pin Capacitance V
I/O
=0V 12 pF
C
IN
1
Input Capacitance V
IN
=0V 12 pF
T16.0 25026
1. This parameter is measured only for initial qualification and after a design or process change that could affect this
parameter.
Table 17: Reliability Characteristics
Symbol Parameter
Minimum
Specification Units Test Method
N
END
1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this
parameter.
Endurance 10,000 Cycles JEDEC Standard A117
T
DR
1
Data Retention 100 Years JEDEC Standard A103
I
LTH
1
Latch Up 100 + I
DD
mA JEDEC Standard 78
T17.0 25026
Table 18: Clock Timing Parameters (LPC Mode)
Symbol Parameter Min Max Units
T
CYC
LCLK Cycle Time 30 ns
T
HIGH
LCLK High Time 11 ns
T
LOW
LCLK Low Time 11 ns
- LCLK Slew Rate (peak-to-peak) 1 4 V/ns
- RST# or INIT# Slew Rate 50 mV/ns
T18.0 25026
1235 F12.0
0.4 V
DD
p-to-p
(minimum)
T
cyc
T
high
T
low
0.4 V
DD
0.3 V
DD
0.6 V
DD
0.2 V
DD
0.5 V
DD
©2014 Silicon Storage Technology, Inc. DS20005086B 11/14
30
8 Mbit LPC Flash
SST49LF080A
Data Sheet
Figure 14: Reset Timing Diagram (LPC Mode)
Table 19: Reset Timing Parameters, V
DD
=3.0-3.6V (LPC Mode)
Symbol Parameter Min Max Units
T
PRST
V
DD
stable to Reset Low 1 ms
T
KRST
Clock Stable to Reset Low 100 µs
T
RSTP
RST# Pulse Width 100 ns
T
RSTF
RST# Low to Output Float 48 ns
T
RST
1
RST# High to LFRAME# Low 1 µs
T
RSTE
RST# Low to reset during Sector-/Block-Erase or Pro-
gram
10 µs
T19.0 25026
1. There may be additional latency due toT
RSTE
if a reset procedure is performed during a Program or Erase operation.
CLK
V
DD
RST#/INIT#
LFRAME#
LAD[3:0]
1235 F13.0
T
PRST
T
KRST
T
RSTP
T
RSTF
T
RSTE
Sector-/Block-Erase
or Program operation
aborted
T
RST
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P50

SST49LF080A-33-4C-NHE

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Buy SST49LF080A-33-4C-NHE
Manufacturer:
Microchip Technology
Description:
NOR Flash 1M X 8 33MHz
Lifecycle:
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