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SST49LF080A-33-4C-NHE

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P50
©2014 Silicon Storage Technology, Inc. DS20005086B 11/14
22
8 Mbit LPC Flash
SST49LF080A
Data Sheet
Figure 8: Data# Polling Command Sequence (LPC Mode)
1235 F07.0
0000b 011Xb A[11:8] A[7:4] A[3:0] Dn[7:4]
A[15:12]
D[3:0] Tri-State
TA R
Load Address in 8 Clocks
Write the last command (Program or Erase) to the device in LPC mode.
Address
1
1 Clock 1 Clock
1st Start
Memory
Write
Cycle
TA R
SyncData
Start next
Command
1 Clock
1 Clock2 ClocksLoad Data in 2 Clocks
1111b 0000b
0000b
LAD[3:0]
Read the DQ
7
to see if internal write complete or not.
LCLK
LFRAME#
LAD[3:0]
0000b 010Xb A[11:8] A[7:4] A[3:0] D7,xxx
A[15:12]
XXXXbTri-State
TA R
Load Address in 8 Clocks
When internal write complete, the DQ
7
will equal to D7.
Address
1
1 Clock 1 Clock
Start
Memory
Read
Cycle
TA R
Sync Data
Next start
1 Clock
Data out 2 Clocks1 Clock2 Clocks
1111b
0000b
0000b
LFRAME#
LCLK
0000b 010Xb A[11:8] A[7:4] A[3:0]
D7#,xxx
A[15:12]
XXXXbTri-State
TA R
Load Address in 8 Clocks
Address
1
1 Clock 1 Clock
Start
Memory
Read
Cycle
TA R
Sync Data
Next start
1 Clock
Data out 2 Clocks1 Clock2 Clocks
1111b 0000b
0000b
CE#
CE#
A[23:20]
A[19:16]
A[23:20] A[19:16]
A[23:20] A[19:16]
LFRAME#
LAD[3:0]
LCLK
CE#
A[31:28] A[27:24]
A[31:28] A[27:24]
A[31:28] A[27:24]
Note: 1. Address must be within memory address range specified in Table 4.
©2014 Silicon Storage Technology, Inc. DS20005086B 11/14
23
8 Mbit LPC Flash
SST49LF080A
Data Sheet
Figure 9: Toggle Bit Command Sequence (LPC Mode)
1235 F08.0
LFRAME#
LAD[3:0]
0000b 011Xb A[11:8] A[7:4] A[3:0] D[7:4]
A[15:12]
D[3:0] Tri-State
TA R
Load Address in 8 Clocks
Write the last command (Program or Erase) to the device in LPC mode.
Address
1
1 Clock 1 Clock
1st Start
Memory
Write
Cycle
TA R
SyncData
Start next
Command
1 Clock
1 Clock2 ClocksLoad Data in 2 Clocks
1111b 0000b
0000b
LCLK
LFRAME#
LAD[3:0]
0000b 010Xb
X,D6#,XXb
XXXXbTri-State
TA R
Load Address in 8 Clocks
Read the DQ
6
to see if internal write complete or not.
Address
1
1 Clock 1 Clock
Start
Memory
Read
Cycle
TA R
Sync Data
Next start
1 Clock
Data out 2 Clocks1 Clock2 Clocks
1111b 0000b
0000b
LCLK
LFRAME#
LAD[3:0]
0000b 010Xb
X,D6,XXb
XXXXbTri-State
TA R
Load Address in 8 Clocks
When internal write complete, the DQ
6
will stop toggle.
Address
1
1 Clock 1 Clock
Start
Memory
Read
Cycle
TA R
Sync Data
Next start
1 Clock
Data out 2 Clocks1 Clock2 Clocks
1111b 0000b
0000b
CE#
CE#
LCLK
CE#
A[11:8] A[7:4] A[3:0]
A[15:12]
A[11:8] A[7:4] A[3:0]
A[15:12]
A[23:20] A[19:16]
A[23:20] A[19:16]
A[23:20] A[19:16]
A[31:28] A[27:24]
A[31:28] A[27:24]
A[31:28] A[27:24]
Note: 1. Address must be within memory address range specified in Table 4.
©2014 Silicon Storage Technology, Inc. DS20005086B 11/14
24
8 Mbit LPC Flash
SST49LF080A
Data Sheet
Figure 10: Sector-Erase Command Sequence (LPC Mode)
1235 F12.0
LFRAME#
LAD[3:0]
0000b 011Xb 0101b 0101b 0101b 1010b0101b 1010b Tri-State
TA R
Load Address YYYY 5555H in 8 Clocks
Write the 1st command to the device in LPC mode.
Address
1
1 Clock 1 Clock
1st Start
Memory
Write
Cycle
TA R
SyncData
Start next
Command
1 Clock
1 Clock2 ClocksLoad Data AAH in 2 Clocks
1111b 0000b
LCLK
LFRAME#
LAD[3:0]
0000b
011Xb 1010b 1010b 1010b 0101b0010b 0101b Tri-State
TA R
Load Address YYYY 2AAAH in 8 Clocks
Write the 2nd command to the device in LPC mode.
Address
1
1 Clock
1 Clock
2nd Start
Memory
Write
Cycle
TA R
SyncData
Start next
Command
1 Clock
1 Clock2 ClocksLoad Data 55H in 2 Clocks
1111b 0000b
LCLK
LFRAME#
LAD[3:0]
0000b 011Xb 0101b 0101b 0101b 1000b0101b 0000b
Tri-State
TA R
Load Address YYYY 5555H in 8 Clocks
Write the 3rd command to the device in LPC mode.
Address
1
1 Clock 1 Clock
3rd Start
Memory
Write
Cycle
TA R
SyncData
Start next
Command
1 Clock
1 Clock2 ClocksLoad Data 80H in 2 Clocks
1111b 0000b
LCLK
LFRAME#
LAD[3:0]
0000b 011Xb 0101b 0101b 0101b 1010b0101b 1010b Tri-State
TA R
Load Address YYYY 5555H in 8 Clocks
Write the 4th command to the device in LPC mode.
Address
1
1 Clock 1 Clock
4th Start
Memory
Write
Cycle
TA R
SyncData
Start next
Command
1 Clock
1 Clock2 ClocksLoad Data AAH in 2 Clocks
1111b 0000b
LCLK
LFRAME#
LAD[3:0]
0000b 011Xb 1010b 1010b 1010b 0101b0010b 0101b
XXXXb XXXXb XXXXb 0011b
SA
X
0000b
Tri-State
TA R
Load Address YYYY 2AAA in 8 ClocksH
Load Sector Address in 8 Clocks
Write the 5th command to the device in LPC mode.
Address
1
1 Clock 1 Clock
5th
Memory
Write
Cycle
TA R
SyncData
Start next
Command
1 Clock
1 Clock2 ClocksLoad Data 55H in 2 Clocks
Load Data “30” in 2 Clocks
1111b 0000b
LCLK
LFRAME#
LAD[3:0]
0000b 011Xb Tri-State
TA R
Write the 6th command (target sector to be erased) to the device in LPC mode.
SA
X
= Sector Address
Address
1
1 Clock 1 Clock
6th Start
Memory
Write
Cycle
TA R
SyncData
Internal
erase start
Internal
erase start
1 Clock2 Clocks
1111b 0000b
CE#
CE#
CE#
CE#
CE#
LCLK
CE#
A[23:20] A[19:16]
A[23:20] A[19:16]
A[23:20]
A[19:16]
A[23:20] A[19:16]
A[23:20] A[19:16]
A[23:20] A[19:16]
A[31:28] A[27:24]
A[31:28] A[27:24]
A[31:28] A[27:24]
A[31:28] A[27:24]
A[31:28] A[27:24]
A[31:28] A[27:24]
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P50

SST49LF080A-33-4C-NHE

Mfr. #:
Buy SST49LF080A-33-4C-NHE
Manufacturer:
Microchip Technology
Description:
NOR Flash 1M X 8 33MHz
Lifecycle:
New from this manufacturer.
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