©2014 Silicon Storage Technology, Inc. DS20005086B 11/14
37
8 Mbit LPC Flash
SST49LF080A
Data Sheet
Figure 23: Sector-Erase Timing Diagram (PP Mode)
Figure 24: Block-Erase Timing Diagram (PP Mode)
Figure 25: Chip-Erase Timing Diagram (PP Mode)
5555 5555 5555 2AAA SA
X
2AAA
A
14-0
(Internal A
MS-0
)
R/C#
OE#
WE#
DQ
7-0
Internal Erase Starts
AA
55 80 AA 55 30
SA
X
= Sector Address
1235 F22.0
5555 5555 5555 2AAA BA
X
2AAA
A
14-0
(Internal A
MS-0
)
R/C#
OE#
WE#
DQ
7-0
Internal Erase Starts
AA
55 80 AA 55 50
BA
X
= Block Address
1235 F23.0
5555 5555 5555 2AAA 55552AAA
A
14-0
(Internal A
MS-0
)
R/C#
OE#
WE#
DQ
7-0
Internal Erase Starts
AA
55 80 AA 55 10
1235 F24.0
©2014 Silicon Storage Technology, Inc. DS20005086B 11/14
38
8 Mbit LPC Flash
SST49LF080A
Data Sheet
Figure 26: Software ID Entry and Read (PP Mode)
Figure 27: Software ID Exit (PP Mode)
5555 5555 0000 0001
2AAA
A
14-0
(Internal A
MS-0
)
R/C#
OE#
WE#
DQ
7-0
AA
1235 F25.0
Device ID
BF
55
90
T
WP
T
WPH
T
IDA
T
AA
Note: Device ID = 5BH for SST49LF080A
5555 5555
2AAA
A
14-0
(Internal A
MS-0
)
R/C#
OE#
WE#
DQ
7-0
AA
1235 F26.0
55
F0
T
IDA
©2014 Silicon Storage Technology, Inc. DS20005086B 11/14
39
8 Mbit LPC Flash
SST49LF080A
Data Sheet
Figure 28: AC Input/Output Reference Waveforms
Figure 29: A Test Load Example
Figure 30: Read Flowchar t (LPC Mode)
1235 F27.0
REFERENCE POINTS OUTPUTINPUT
V
IT
V
IHT
V
ILT
V
OT
AC test inputs are driven at V
IHT
(0.9 V
DD
) for a logic “1” and V
ILT
(0.1 V
DD
) for a logic “0”. Measure-
ment reference points for inputs and outputs are V
IT
(0.5 V
DD
) and V
OT
(0.5 V
DD
). Input r ise and fall
times (10% 90%) are <3 ns.
Note: V
IT
-V
INPUT
Test
V
OT
-V
OUTPUT
Test
V
IHT
-V
INPUT
HIGH Test
V
ILT
-V
INPUT
LOW Test
1235 F28.0
TO TESTER
TO DUT
C
L
1235 F29.0
Address: A
IN
Read Data: D
OUT
Cycle: 1
Read
Command Sequence
Available for
Next Command

SST49LF080A-33-4C-NHE

Mfr. #:
Manufacturer:
Microchip Technology
Description:
NOR Flash 1M X 8 33MHz
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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