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SST49LF080A-33-4C-NHE

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P50
©2014 Silicon Storage Technology, Inc. DS20005086B 11/14
10
8 Mbit LPC Flash
SST49LF080A
Data Sheet
INIT#, RST#
AV
IL
on INIT# or RST# pin initiates a device reset. INIT# and RST# pins have the same function
internally. It is required to drive INIT# or RST# pins low during a system reset to ensure proper
CPU initialization. During a Read operation, driving INIT# or RST# pins low deselects the device
and places the output drivers, LAD[3:0], in a high-impedance state. The reset signal must be held
low for a minimal duration of time T
RSTP
. A reset latency will occur if a reset procedure is performed
during a Program or Erase operation. See Table 19, Reset Timing Parameters for more informa-
tion. A device reset during an active Program or Erase will abort the operation and memory con-
tents may become invalid due to data being altered or corrupted from an incomplete Erase or
Program operation.
System Memory Mapping
The LPC interface protocol has address length of 32-bit or 4 GByte. The SST49LF080A will
respond to addresses in the range as specified in Table 4.
Refer to “Multiple Device Selection” section for more detail on strapping multiple SST49LF080A
devices to increase memory densities in a system and “Registers” section on valid register
addresses.
Table 4: Address Decoding Range
ID Strapping Device Access Address Range Memory Size
Device #0 - 3 Memory Access FFFF FFFFH : FFC0 0000H 4 MByte
Register Access FFBF FFFFH : FF80 0000H 4 MByte
Device #4 - 7 Memory Access FF7F FFFFH : FF40 0000H 4 MByte
Register Access FF3F FFFFH : FF00 0000H 4 MByte
Device #8 - 11 Memory Access FEFF FFFFH : FEC0 0000H 4 MByte
Register Access FEBF FFFFH : FE80 0000H 4 MByte
Device #12 - 15 Memory Access FE7F FFFFH : FE40 0000H 4 MByte
Register Access FE3F FFFFH : FE00 0000H 4 MByte
Device #0
1
1. For device #0 (Boot Device), SST49LF080A decodes the physical addresses of the top 2 blocks (including Boot
Block) both at
system memory ranges FFFF FFFFH to FFFE 0000H and 000F FFFFH to 000E 0000H.
Memory Access 000F FFFFH : 000E 0000H 128 KByte
T4.0 25026
©2014 Silicon Storage Technology, Inc. DS20005086B 11/14
11
8 Mbit LPC Flash
SST49LF080A
Data Sheet
Figure 5: LPC Read Cycle Wavefor m
Table 5: LPC Read Cycle
Clock
Cycle
Field
Name
Field
Contents
LAD[3:0]
1
LAD[3:0]
Direction Comments
1 START 0000 IN LFRAME# must be active (low) for the part to respond.
Only the last start field (before LFRAME# transitions
high) should be recognized.
2 CYCTYPE
+ DIR
010X IN Indicates the type of cycle. Bits 3:2 must be “01b” for memory
cycle. Bit 1 indicates the type of transf er “0” for Read. Bit 0 is
reserv ed.
3-10 ADDRESS YYYY IN Address Phase for Memory Cycle. LPC protocol sup-
ports a 32-bit address phase. YYYY is one nibble of the
entire address. Addresses are transferred most-signifi-
cant nibble fist. See Table 3 for address bits definition
and Table 4 for valid memory address range.
11 TAR0 1111 IN
then Float
In this clock cycle, the host has driven the bus to all 1s
and then floats the bus. This is the first part of the bus
“turnaround cycle.”
12 TAR1 1111 (float) Float
then OUT
The SST49LF080A takes control of the bus during this
cycle
13 SYNC 0000 OUT The SST49LF080A outputs the value 0000b indicating
that data will be available during the next clock cycle.
14 DATA ZZZZ OUT This field is the least-significant nibb le of the data byte .
15 DATA ZZZZ OUT This field is the most-significant nibb le of the data byte .
16 TAR0 1111 OUT
then Float
In this clock cycle, the SST49LF080A has driven the bus
to all 1s and then floats the bus. This is the first part of
the bus “turnaround cycle.”
17 TAR1 1111 (float) Float
then IN
The host takes control of the bus during this cycle
T5.0 25026
1. Field contents are valid on the rising edge of the present clock cycle.
1235 F04.0
LCLK
CE#
LFRAME#
LAD[3:0]
0000b 010Xb
A[23:20]
A[19:16]
A[3:0]A[7:4]A[11:8]A[15:12] 1111b Tri-State
2Clocks
TA R 0
Load Address in 8 Clocks
Address
1Clock 1Clock
Start
CYCTYPE
+
DIR
TA R
1Clock
Sync Data
Data Out 2 Clocks
0000b D[7:4]D[3:0]
A[31:28] A[27:24]
TA R 1
©2014 Silicon Storage Technology, Inc. DS20005086B 11/14
12
8 Mbit LPC Flash
SST49LF080A
Data Sheet
Figure 6: LPC Write Cycle Waveform
Table 6: LPC Write Cycle
Clock
Cycle
Field
Name
Field
Contents
LAD[3:0]
1
LAD[3:0]
Direction Comments
1 START 0000 IN LFRAME# must be active (low) for the part to
respond. Only the last start field (before
LFRAME# transitions high) should be recog-
nized.
2 CYCTYPE
+ DIR
011X IN Indicates the type of cycle. Bits 3:2 must be
“01b” for memor y cycle. Bit 1 indicates the
type of transfer “1” for Wr ite. Bit 0 is reserved.
3-10 ADDRESS YYYY IN Address Phase for Memory Cycle. LPC protocol
supports a 32-bit address phase. YYYY is one
nibble of the entire address. Addresses are
transferred most-significant nibble first. See
Table 3 for address bits definition and Table 4 for
valid memory address range.
11 DATA ZZZZ IN This field is the least-significant nibble of the data
byte.
12 DATA ZZZZ IN This field is the most-significant nibble of the
data byte.
13 TAR0 1111 IN then Float In this clock cycle, the host has driven the bus to
all ‘1’s and then floats the bus. This is the first
part of the bus “turnaround cycle.”
14 TAR1 1111 (float) Float then
OUT
The SST49LF080A takes control of the bus dur-
ing this cycle.
15 SYNC 0000 OUT The SST49LF080A outputs the values 0000, indicat-
ing that it has received data or a flash command.
16 TAR0 1111 OUT then
Float
In this clock cycle, the SST49LF080A has driven
the bus to all ‘1’s and then floats the bus. This is
the first part of the bus “turnaround cycle.”
17 TAR1 1111 (float) Float then IN Host resumes control of the bus during this cycle.
T6.0 25026
1. Field contents are valid on the rising edge of the present clock cycle.
1235 F05.0
LFRAME#
LAD[3:0]
0000b 011Xb A[23:20]
A[19:16]
A[3:0]A[7:4]A[11:8]A[15:12] 1111b Tri-State
2Clocks
TA R 0
Load Address in 8 Clocks
Address
1Clock 1Clock
Start
CYCTYPE
+
DIR
TA R
1Clock
Sync
Data
Load Data in 2 Clocks
0000bD[7:4]D[3:0]
LCLK
CE#
A[31:28] A[27:24]
Data
TA R 1
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P50

SST49LF080A-33-4C-NHE

Mfr. #:
Buy SST49LF080A-33-4C-NHE
Manufacturer:
Microchip Technology
Description:
NOR Flash 1M X 8 33MHz
Lifecycle:
New from this manufacturer.
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