©2014 Silicon Storage Technology, Inc. DS20005086B 11/14
31
8 Mbit LPC Flash
SST49LF080A
Data Sheet
AC Characteristics
Table 20: Read/Wr ite Cycle Timing Parameters, V
DD
=3.0-3.6V (LPC Mode)
Symbol Parameter Min Max Units
T
CYC
Clock Cycle Time 30 ns
T
SU
Data Set Up Time to Clock Rising 7 ns
T
DH
Clock Rising to Data Hold Time 0 ns
T
VAL
1
1. Minimum and maximum times have different loads. See PCI spec.
Clock Rising to Data Valid 2 11 ns
T
BP
Byte Programming Time 20 µs
T
SE
Sector-Erase Time 25 ms
T
BE
Block-Erase Time 25 ms
T
ON
Clock Rising to Active (Float to Active Delay) 2 ns
T
OFF
Clock Rising to Inactive (Active to Float Delay) 28 ns
T20.0 25026
Table 21: AC Input/Output Specifications (LPC Mode)
Symbol Parameter Min Max Units Conditions
I
OH
(AC) Switching Current
High
-12 V
DD
-17.1(V
DD
-V
OUT
)
Equation
C
1
1. See PCI spec.
mA
mA
0<V
OUT
0.3 V
DD
0.3 V
DD
<V
OUT
< 0.9 V
DD
0.7 V
DD
<V
OUT
<V
DD
(Test Point) -32 V
DD
mA V
OUT
= 0.7 V
DD
I
OL
(AC) Switching Current
Low
16 V
DD
26.7 V
OUT
Equation
D
1
mA
mA
V
DD
>V
OUT
0.6 V
DD
0.6 V
DD
>V
OUT
> 0.1 V
DD
0.18 V
DD
>V
OUT
>0
(Test Point) 38 V
DD
mA V
OUT
= 0.18 V
DD
I
CL
Low Clamp Current -25+(V
IN
+1)/0.015 mA -3 < V
IN
-1
I
CH
High Clamp Current 25+(V
IN
-V
DD
-1)/0.015 mA V
DD
+4 > V
IN
V
DD
+1
slewr
2
2. PCI specification output load is used.
Output Rise Slew
Rate
1 4 V/ns 0.2 V
DD
-0.6 V
DD
load
slewf
2
Output Fall Slew
Rate
1 4 V/ns 0.6 V
DD
-0.2 V
DD
load
T21.0 25026
©2014 Silicon Storage Technology, Inc. DS20005086B 11/14
32
8 Mbit LPC Flash
SST49LF080A
Data Sheet
Figure 15: Output Timing Parameters (LPC Mode)
Figure 16: Input Timing Parameters (LPC Mode)
Table 22: Interface Measurement Condition Parameters (LPC Mode)
Symbol Value Units
V
TH
1
1. The input test environment is done with 0.1 V
DD
of overdrive over V
IH
and V
IL
. Timing parameters must be met with no
more overdrive than this. V
MAX
specified the maximum peak-to-peak waveform allowed for measuring input timing. Pro-
duction testing may use different voltage values, but must correlate results back to these parameters
0.6 V
DD
V
V
TL
1
0.2 V
DD
V
V
TEST
0.4 V
DD
V
V
MAX
1
0.4 V
DD
V
Input Signal Edge Rate 1 V/ns
T22.0 25026
T
VAL
T
OFF
T
ON
1235 F14.0
LCLK
LAD [3:0]
(Valid Output Data)
LAD [3:0]
(Float Output Data)
V
TEST
V
TL
V
TH
T
SU
T
DH
Inputs
Valid
1235 F15.0
LCLK
LAD [3:0]
(Valid Input Data)
V
TEST
V
TL
V
MAX
V
TH
©2014 Silicon Storage Technology, Inc. DS20005086B 11/14
33
8 Mbit LPC Flash
SST49LF080A
Data Sheet
Table 23: Read Cycle Timing Parameters, V
DD
=3.0-3.6V (PP Mode)
Symbol Parameter Min Max Units
T
RC
Read Cycle Time 270 ns
T
RST
RST# High to Row Address Setup 1 µs
T
AS
R/C# Address Set-up Time 45 ns
T
AH
R/C# Address Hold Time 45 ns
T
AA
Address Access Time 120 ns
T
OE
Output Enable Access Time 60 ns
T
OLZ
OE# Low to Active Output 0 ns
T
OHZ
OE# High to High-Z Output 35 ns
T
OH
Output Hold from Address Change 0 ns
T23.0 25026
Table 24: Program/Erase Cycle Timing Parameters, V
DD
=3.0-3.6V (PP Mode)
Symbol Parameter Min Max Units
T
RST
RST# High to Row Address Setup 1 µs
T
AS
R/C# Address Setup Time 50 ns
T
AH
R/C# Address Hold Time 50 ns
T
CWH
R/C# to Write Enable High Time 50 ns
T
OES
OE# High Setup Time 20 ns
T
OEH
OE# High Hold Time 20 ns
T
OEP
OE# to Data# Polling Delay 40 ns
T
OET
OE# to Toggle Bit Delay 40 ns
T
WP
WE# Pulse Width 100 ns
T
WPH
WE# Pulse Width High 100 ns
T
DS
Data Setup Time 50 ns
T
DH
Data Hold Time 5 ns
T
IDA
Software ID Access and Exit Time 150 ns
T
BP
Byte Programming Time 20 µs
T
SE
Sector-Erase Time 25 ms
T
BE
Block-Erase Time 25 ms
T
SCE
Chip-Erase Time 100 ms
T24.0 25026

SST49LF080A-33-4C-NHE

Mfr. #:
Manufacturer:
Microchip Technology
Description:
NOR Flash 1M X 8 33MHz
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union