DATASHEET
5P1103 REVISION D 07/13/15 1 ©2015 Integrated Device Technology, Inc.
Programmable Fanout Buffer 5P1103
Description
The 5P1103 is a programmable fanout buffer intended for
high performance consumer, networking, industrial,
computing, and data-communications applications.
Configurations may be stored in on-chip One-Time
Programmable (OTP) memory or changed using I
2
C
interface.
The outputs are generated from a single reference clock. The
input reference can be crystal, external single-ended or
differential clock. The reference clock can come from one of
the two redundant clock inputs and is selected by CLKSEL
pin. A glitchless manual switchover function allows one of the
redundant clocks to be selected during normal operation. See
reference clock input section for details.
Two select pins allow up to 4 different configurations to be
programmed and accessible using processor GPIOs or
bootstrapping. The different selections may be used for
different operating modes (full function, partial function, partial
power-down), regional standards (US, Japan, Europe) or
system production margin testing.
The device may be configured to use one of two I
2
C
addresses to allow multiple devices to be used in a system.
Pin Assignment
Features
Up to two high performance universal differential output
pairs
– Low RMS additive phase jitter: 0.2ps
Four banks of internal non-volatile in-system
programmable or factory programmable OTP memory
I
2
C serial programming interface
One additional LVCMOS output clock
Two universal output pairs:
– Each configurable as one differential output pair or two
LVCMOS outputs
I/O Standards:
– Single-ended I/Os: 1.8V to 3.3V LVCMOS
– Differential I/Os - LVPECL, LVDS and HCSL
Input frequency ranges:
– LVCMOS Reference Clock Input (XIN/REF) – 1MHz to
200MHz
– LVDS, LVPECL, HCSL Differential Clock Input (CLKIN,
CLKINB) – 1MHz to 350MHz
– Crystal frequency range: 8MHz to 40MHz
Individually selectable output voltage (1.8V, 2.5V, 3.3V) for
each output pair
Redundant clock inputs with manual switchover
Programmable crystal load capacitance
Individual output enable/disable
Power-down mode
1.8V, 2.5V or 3.3V core V
DDD
, V
DDA
Available in 24-pin VFQFPN 4mm x 4mm package
-40° to +85°C industrial temperature operation
1
7
24-pin VFQFPN
19
13
XOUT
XIN/REF
V
DDA
CLKIN
NC
OUT2
CLKINB
CLKSEL
NC
OUT2B
V
DDO
2
V
DDA
SD/OE
SEL1/SDA
SEL0/SCL
V
DDA
NC
NC
OUT1B
OUT1
V
DDO
1
V
DDD
V
DDO
0
OUT0_SEL_I2CB
EPAD
2
3
4
5
6
8
9
10 11
12
14
15
16
17
18
2021222324
PROGRAMMABLE FANOUT BUFFER 2 REVISION D 07/13/15
5P1103 DATASHEET
Functional Block Diagram
Applications
Ethernet switch/router
PCI Express 1.0/2.0/3.0
Broadcast video/audio timing
Multi-function printer
Processor and FPGA clocking
MSAN/DSLAM/PON
Fiber Channel, SAN
Telecom line cards
1 GbE and 10 GbE
XIN/REF
XOUT
CLKIN
CLKINB
CLKSEL
SD/OE
SEL1/SDA
SEL0/SCL
V
DDA
V
DDD
V
DDO
0
OUT0_SEL_I2CB
V
DDO
1
OUT1
OUT1B
V
DDO
2
OUT2
OUT2B
V
DDA
V
DDA
OTP
and
Control Logic
REVISION D 07/13/15 3 PROGRAMMABLE FANOUT BUFFER
5P1103 DATASHEET
Table 1:Pin Descriptions
Number Name Description
1 CLKIN Input Pull-down Differential clock input. Weak 100kohms internal pull-down.
2 CLKINB Input Pull-down Complementary differential clock input. Weak 100kohms internal pull-down.
3 XOUT Input Crystal Oscillator interface output.
4 XIN/REF Input
Crystal Oscillator interface input, or single-ended LVCMOS clock input. Ensure
that the input voltage is 1.2V max. Refer to the section “Overdriving the XIN/REF
Interface”.
5 VDDA Power
Analog functions power supply pin. Connect to 1.8V to 3.3V. VDDA and VDDD
should have the same voltage applied.
6 CLKSEL Input Pull-down
Input clock select. Selects the active input reference source, when in Manual
switchover mode.
0 = XIN/REF, XOUT (default)
1 = CLKIN, CLKINB
CLKSEL Polarity can be changed by I2C programming as shown in Table 4.
7 SD/OE Input Pull-down
Enables/disables the outputs (OE) or powers down the chip (SD). The SH bit
controls the configuration of the SD/OE pin. The SH bit needs to be high for
SD/OE pin to be configured as SD. The SP bit (0x02) controls the polarity of the
signal to be either active HIGH or LOW only when pin is configured as OE
(Default is active LOW.) Weak internal pull down resistor. When configured as
SD, device is shut down, differential outputs are driven high/low, and the single-
ended LVCMOS outputs are driven low. When configured as OE, and outputs are
disabled, the outputs can be selected to be tri-stated or driven high/low,
depending on the programming bits as shown in the SD/OE Pin Function Truth
table.
8 SEL1/SDA Input Pull-down
Configuration select pin, or I2C SDA input as selected by OUT0_SEL_I2CB.
Weak internal pull down resistor.
9 SEL0/SCL Input Pull-down
Configuration select pin, or I2C SCL input as selected by OUT0_SEL_I2CB.
Weak internal pull down resistor.
10 VDDA Power
Analog functions power supply pin. Connect to 1.8V to 3.3V. VDDA and VDDD
should have the same voltage applied.
11 NC No connect.
12 NC No connect.
13 NC No connect.
14 NC No connect.
15 VDDA Power
Analog functions power supply pin. Connect to 1.8V to 3.3V. VDDA and VDDD
should have the same voltage applied.
16 OUT2B Output
Complementary Output Clock 2. Please refer to the Output Drivers section for
more details.
17 OUT2 Output Output Clock 2. Please refer to the Output Drivers section for more details.
18 VDDO2 Power
Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for
OUT2/OUT2B.
19 OUT1B Output
Complementary Output Clock 1. Please refer to the Output Drivers section for
more details.
20 OUT1 Output Output Clock 1. Please refer to the Output Drivers section for more details.
21 VDDO1 Power
Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for
OUT1/OUT1B.
22 VDDD Power
Digital functions power supply pin. Connect to 1.8 to 3.3V. VDDA and VDDB
should have the same voltage applied.
23 VDDO0 Power
Power supply pin for OUT0_SEL_I2CB. Connect to 1.8 to 3.3V. Sets output
voltage levels for OUT0.
24 OUT0_SELB_I2C Input/Output Pull-down
Latched input/LVCMOS Output. At power up, the voltage at the pin
OUT0_SEL_I2CB is latched by the part and used to select the state of pins 8
and 9. If a weak pull up (10Kohms) is placed on OUT0_SEL_I2CB, pins 8 and 9
will be configured as hardware select pins, SEL1 and SEL0. If a weak pull down
(10Kohms) is placed on OUT0_SEL_I2CB or it is left floating, pins 8 and 9 will
act as the SDA and SCL pins of an I2C interface. After power up, the pin acts as
a LVCMOS reference output.
ePAD VEE Power Connect to ground pad.
Type

5P1103A000NLGI

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer 2 to 4 Output OTP 1.8 to 3.3V Prog Out
Lifecycle:
New from this manufacturer.
Delivery:
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