REVISION D 07/13/15 19 PROGRAMMABLE FANOUT BUFFER
5P1103 DATASHEET
Overdriving the XIN/REF Interface
LVCMOS Driver
The XIN/REF input can be overdriven by an LVCMOS driver
or by one side of a differential driver through an AC coupling
capacitor. The XOUT pin can be left floating. The amplitude of
the input signal should be between 500mV and 1.2V and the
slew rate should not be less than 0.2V/ns. Figure General
Diagram for LVCMOS Driver to XTAL Input Interface shows an
example of the interface diagram for a LVCMOS driver.
This configuration has three properties; the total output
impedance of Ro and Rs matches the 50 ohm transmission
line impedance, the Vrx voltage is generated at the CLKIN
inputs which maintains the LVCMOS driver voltage level
across the transmission line for best S/N and the R1-R2
voltage divider values ensure that the clock level at XIN is less
than the maximum value of 1.2V.
General Diagram for LVCMOS Driver to XTAL Input
Interface
Table 21 Nominal Voltage Divider Values vs LVCMOS VDD for
XIN
shows resistor values that ensure the maximum drive
level for the XIN/REF port is not exceeded for all combinations
of 5% tolerance on the driver VDD, the VDDA and 5% resistor
tolerances. The values of the resistors can be adjusted to
reduce the loading for slower and weaker LVCMOS driver by
increasing the voltage divider attenuation as long as the
minimum drive level is maintained over all tolerances. To
assist this assessment, the total load on the driver is included
in the table.
Table 21:Nominal Voltage Divider Values vs LVCMOS VDD for XIN
XOUT
XIN / REF
R1
R2
C3
0. 1 uF
V_XIN
LV CMOS
VDD
Ro
Ro + Rs = 50 ohms
Rs Zo = 50 Ohm
LVCMOS Driver VDD Ro+Rs R1 R2 V_XIN (peak) Ro+Rs+R1+R2
3.3 50.0 130 75 0.97 255
2.5 50.0 100 100 1.00 250
1.8 50.0 62 130 0.97 242
PROGRAMMABLE FANOUT BUFFER 20 REVISION D 07/13/15
5P1103 DATASHEET
LVPECL Driver
Figure General Diagram for LVPECL Driver to XTAL Input
Interface shows an example of the interface diagram for a
+3.3V LVPECL driver. This is a standard LVPECL termination
with one side of the driver feeding the XIN/REF input. It is
recommended that all components in the schematics be
placed in the layout; though some components might not be
used, they can be utilized for debugging purposes. The
datasheet specifications are characterized and guaranteed by
using a quartz crystal as the input. If the driver is 2.5V
LVPECL, the only change necessary is to use the appropriate
value of R3.
General Diagram for +3.3V LVPECL Driver to XTAL Input Interface
CLKIN Equivalent Schematic
Figure CLKIN Equivalent Schematic below shows the basis of
the requirements on VIH max, VIL min and the 1200 mV p-p
single ended Vswing maximum.
The CLKIN and CLKINB Vih max spec comes from the
cathode voltage on the input ESD diodes D2 and D4, which
are referenced to the internal 1.2V supply. CLKIN or
CLKINB voltages greater than 1.2V + 0.5V =1.7V will be
clamped by these diodes. CLKIN and CLKINB input
voltages less than -0.3V will be clamped by diodes D1 and
D3.
The 1.2V p-p maximum Vswing input requirement is
determined by the internally regulated 1.2V supply for the
actual clock receiver. This is the basis of the Vswing spec in
Table 13.
+3 .3 V LVPE CL D r iv er
Zo = 50 Ohm
Zo = 50 Ohm
R1
50
R2
50
R3
50
XOUT
XIN / REF
C1
0. 1 uF
REVISION D 07/13/15 21 PROGRAMMABLE FANOUT BUFFER
5P1103 DATASHEET
CLKIN Equivalent Schematic
Wiring the Differential Input to Accept Single-Ended Levels
Figure Recommended Schematic for Wiring a Differential
Input to Accept Single-ended Levels
shows how a differential
input can be wired to accept single ended levels. This
configuration has three properties; the total output impedance
of Ro and Rs matches the 50 ohm transmission line
impedance, the Vrx voltage is generated at the CLKIN inputs
which maintains the LVCMOS driver voltage level across the
transmission line for best S/N and the R1-R2 voltage divider
values ensure that Vrx p-p at CLKIN is less than the maximum
value of 1.2V.
Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
R1
R2
Vrx
VersaClock 5 Receiver
CLKI N
CLKI NB
LV CMOS
VDD
Zo = 50 Ohm
Ro + Rs = 50
Rs
Ro

5P1103A000NLGI

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Manufacturer:
IDT
Description:
Clock Buffer 2 to 4 Output OTP 1.8 to 3.3V Prog Out
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