MAX1712EEG Datasheet MAX1710EEG, MAX1711EEG, MAX1712EEG | P16-P18

MAX1710/MAX1711/MAX1712

High-Speed, Digitally Adjusted

Step-Down Controllers for Notebook CPUs

16 ______________________________________________________________________________________

pullups on each input in order to eliminate external resis-

tors.

When changing MAX1710 DAC codes while powered

up, the over/undervoltage protection features can be

activated if the code is changed more than 1LSB at a

time. For applications needing the capability of changing

DAC codes “on-the-fly,” use the MAX1711/MAX1712.

POR, UVLO, and Soft-Start

Power-on reset (POR) occurs when V

rises above

approximately 2V, resetting the fault latch and soft-start

counter, and preparing the PWM for operation. V

undervoltage lockout (UVLO) circuitry inhibits switching

and forces the DL gate driver high (in order to enforce

output overvoltage protection) until V

rises above

4.2V, whereupon an internal digital soft-start timer begins

to ramp up the maximum allowed current limit. The ramp

occurs in five steps: 20%, 40%, 60%, 80%, and 100%,

with 100% current available after 1.7ms ±50%.

A continuously adjustable, analog soft-start function can

be realized by adding a capacitor in parallel with R

LIM

ILIM. This soft-start method requires a minimum interval

between power-down and power-up to allow R

LIM

to dis-

charge the capacitor.

Power-Good Output (PGOOD)

The output (FB) is continuously monitored for undervolt-

age by the PGOOD comparator, except in shutdown or

standby mode. The -5% undervoltage trip threshold is

measured with respect to the nominal unloaded output

voltage, as set by the DAC. If the DAC code increases in

steps greater than 1LSB, it is likely that PGOOD will

momentarily go low. In shutdown and standby modes,

PGOOD is actively held low. The PGOOD output is a true

SHDN SKIP OVP

DL MODE COMMENTS

1 X

0 X 0 High Shutdown1 Low-power shutdown state. DL is forced to V

, enforcing OVP. I

< 1µA typ.

X Low

0 X 1 Low Shutdown2

Low-power shutdown state. DL is forced to GND, disabling OVP. I

< 1µA typ.

Exiting shutdown triggers a soft-start cycle.

Shutdown3

(MAX1711/

MAX1712)

DAC code = X1111 (MAX1711), DAC code = 11111 (MAX1712) (Table 2). DL is

forced to PGND, DH is forced to LX. The MAX1711/MAX1712 eventually goes

into UVP fault mode as the load current discharges the output.

Below

GND

X Switching No fault

Test mode with OVP, UVP, and thermal faults disabled and latches cleared.

Otherwise normal operation, with automatic PWM/PFM switchover for pulse

skipping at light loads (Figure 6).

1 X 1 Switching No OVP

OVP faults disabled and OVP latch cleared. Otherwise normal operation,

with SKIP controlling PWM/PFM switchover.

1 V

X Switching

Run (PWM),

Low Noise

Low-noise operation with no automatic switchover. Fixed-frequency PWM action

is forced regardless of load. Inductor current reverses at light load levels.

draw = 750µA typ. I

draw = 15mA typ.

1 GND X Switching

Run

(PFM/PWM)

Normal operation with automatic PWM/PFM switchover for pulse skipping at light

loads. I

= 600µA typ. I

draw = load dependent.

1 X X High Fault

Fault latch has been set by OVP, output UVLO, or thermal shutdown. Device will

remain in FAULT mode until V

power is cycled, SKIP is forced below ground,

or SHDN is toggled.

Table 4. Operating Mode Truth Table

Good operating point for

compound buck designs

or desktop circuits.

+5V-input notebook

CPU core

550

400

3-cell Li+ notebook

CPU core

Useful in 4-cell systems

for lighter loads than the

CPU or where size is key.

Considered mainstream

by current standards.

4-cell Li+ notebook

CPU core

300

Table 5. Frequency Selection Guidelines

FREQUENCY

(kHz)

TYPICAL

APPLICATION

COMMENT

200

4-cell Li+ notebook

CPU core

Use for absolute best

efficiency.

MAX1710/MAX1711/MAX1712

______________________________________________________________________________________ 17

High-Speed, Digitally Adjusted

Step-Down Controllers for Notebook CPUs

open-drain type with no parasitic ESD diodes. Note that

the PGOOD undervoltage detector is completely inde-

pendent of the output UVP fault detector.

Output Overvoltage Protection (OVP)

The OVP circuit is designed to protect against a short-

ed high-side MOSFET by drawing high current and

blowing the battery fuse. The FB node is continuously

monitored for overvoltage. The overvoltage trip thresh-

old tracks the DAC code setting. If the output is more

than 12.5% above the nominal regulation point for

the MAX1710 (2.25V absolute for the MAX1711/

MAX1712), overvoltage protection OVP is triggered and

the circuit shuts down. The DL low-side gate-driver out-

put is then latched high until SHDN is toggled or V

power is cycled below 1V. This action turns on the syn-

chronous-rectifier MOSFET with 100% duty and, in turn,

rapidly discharges the output filter capacitor and forces

the output to ground.

If the condition that caused the overvoltage (such as a

shorted high-side MOSFET) persists, the battery fuse will

blow. Note that DL going high can have the effect of

causing output polarity reversal, due to energy stored in

the output LC at the instant OVP activates. If the load

can’t tolerate being forced to a negative voltage, it may

be desirable to place a power Schottky diode across the

output to act as a reverse-polarity clamp (Figure 1). The

MAX1710/MAX1711/MAX1712 themselves can be

affected by the FB pin going below ground, with the neg-

ative voltage coupling into SHDN. It may be necessary to

add 1kΩ resistors in series with FB and FBS (Figure 7).

DL is also kept high continuously when V

UVLO is

active as well as in Shutdown1 mode (Table 4).

Overvoltage protection can be defeated via the OVP

input (MAX1710 only) or via a SKIP test mode (see Pin

Description).

Output Undervoltage Protection (UVP)

The output UVP function is similar to foldback current

limiting, but employs a timer rather than a variable cur-

rent limit. If the MAX1710 output (FB) is under 70% of the

nominal value 20ms after coming out of shutdown, the

PWM is latched off and won’t restart until V

power is

cycled or SHDN is toggled. For the MAX1711/MAX1712,

the nominal UVP trip threshold is fixed at 0.8V.

No-Fault Test Mode

The over/undervoltage protection features can compli-

cate the process of debugging prototype breadboards

since there are (at most) a few milliseconds in which to

determine what went wrong. Therefore, a test mode is

provided to totally disable the OVP, UVP, and thermal

shutdown features, and clear to the fault latch if it has

been previously set. The PWM operates as if SKIP were

grounded (PFM/PWM mode).

The no-fault test mode is entered by sinking 1.5mA

from SKIP via an external negative voltage source in

series with a resistor (Figure 6). SKIP is clamped to

GND with a silicon diode, so choose the resistor value

equal to (V

FORCE

- 0.65V) / 1.5mA.

Design Procedure

Firmly establish the input voltage range and maximum

load current before choosing a switching frequency and

inductor operating point (ripple current ratio). The prima-

ry design trade-off lies in choosing a good switching fre-

quency and inductor operating point, and the following

four factors dictate the rest of the design:

1) Input voltage range. The maximum value (V

BATT

(MAX)

) must accommodate the worst-case high AC

adapter voltage. The minimum value (V

BATT(MIN)

)

must account for the lowest battery voltage after

drops due to connectors, fuses, and battery selector

switches. If there is a choice at all, lower input volt-

ages result in better efficiency.

2) Maximum load current. There are two values to con-

sider. The peak load current (I

LOAD(MAX)

) determines

the instantaneous component stresses and filtering

requirements, and thus drives output capacitor

selection, inductor saturation rating, and the design

of the current-limit circuit. The continuous load cur-

rent (I

LOAD

) determines the thermal stresses and

thus drives the selection of input capacitors,

MOSFETs, and other critical heat-contributing com-

ponents. Modern notebook CPUs generally exhibit

LOAD

= I

LOAD(MAX)

80%.

3) Switching frequency. This choice determines the

basic trade-off between size and efficiency. The opti-

mal frequency is largely a function of maximum input

APPROXIMATELY

-0.65V

1.5mA

FORCE

SKIP

GND

MAX1710

MAX1711

MAX1712

Figure 6. Disabling Over/Undervoltage Protection (Test Mode)

MAX1710/MAX1711/MAX1712

High-Speed, Digitally Adjusted

Step-Down Controllers for Notebook CPUs

18 ______________________________________________________________________________________

voltage, due to MOSFET switching losses that are

proportional to frequency and VBATT

. The optimum

frequency is also a moving target, due to rapid

improvements in MOSFET technology that are making

higher frequencies more practical (Table 5).

4) Inductor operating point. This choice provides

trade-offs between size vs. efficiency. Low inductor

values cause large ripple currents, resulting in the

smallest size, but poor efficiency and high output

noise. The minimum practical inductor value is one

that causes the circuit to operate at the edge of criti-

cal conduction (where the inductor current just touch-

es zero with every cycle at maximum load). Inductor

values lower than this grant no further size-reduction

benefit.

The MAX1710/MAX1711/MAX1712s’ pulse-skipping

algorithm initiates skip mode at the critical-conduction

point. So, the inductor operating point also determines

the load-current value at which PFM/PWM switchover

occurs. The optimum point is usually found between

20% and 50% ripple current.

The inductor ripple current also impacts transient-

response performance, especially at low V

BATT

- V

OUT

differentials. Low inductor values allow the inductor cur-

rent to slew faster, replenishing charge removed from the

output filter capacitors by a sudden load step. The

amount of output sag is also a function of the maximum

duty factor, which can be calculated from the on-time

and minimum off-time:

Inductor Selection

The switching frequency (on-time) and operating point

(% ripple or LIR) determine the inductor value as follows:

Example: I

LOAD(MAX)

= 7A, V

OUT

= 2V, f = 300kHz, 50%

ripple current or LIR = 0.5:

Find a low-loss inductor having the lowest possible DC

resistance that fits in the allotted dimensions. Ferrite

cores are often the best choice, although powdered iron

is cheap and can work well at 200kHz. The core must be

large enough not to saturate at the peak inductor current

PEAK

= I

LOAD(MAX)

+ (LIR / 2)

LOAD(MAX)

Setting the Current Limit

The minimum current-limit threshold must be great

enough to support the maximum load current when the

current limit is at the minimum tolerance value. The valley

of the inductor current occurs at I

LOAD(MAX)

minus half

of the ripple current, therefore:

LIMIT(LOW)

> I

LOAD(MAX)

- (LIR / 2)

LOAD(MAX)

where I

LIMIT(LOW)

= minimum current-limit threshold volt-

age divided by the R

DS(ON)

of Q2. For the MAX1710, the

minimum current-limit threshold (100mV default setting)

is 90mV. Use the worst-case maximum value for R

DS(ON)

from the MOSFET Q2 data sheet, and add some margin

for the rise in R

DS(ON)

with temperature. A good general

rule is to allow 0.5% additional resistance for each °C of

temperature rise.

Examining the 7A notebook CPU circuit example with a

maximum R

DS(ON)

= 15mΩ at high temperature reveals

the following:

LIMIT(LOW)

= 90mV / 15mΩ = 6A

6A is greater than the valley current of 5.25A, so the cir-

cuit can easily deliver the full rated 7A using the default

100mV nominal ILIM threshold.

When adjusting the current limit, use a 1% tolerance R

LIM

resistor to prevent a significant increase of errors in the

current-limit tolerance.

Output Capacitor Selection

The output filter capacitor must have low enough effective

series resistance (ESR) to meet output ripple and load-

transient requirements, yet have high enough ESR to sat-

isfy stability requirements. Also, the capacitance value

must be high enough to absorb the inductor energy

going from a full-load to no-load condition without tripping

the OVP circuit.

In CPU V

CORE

converters and other applications where

the output is subject to violent load transients, the output

capacitor’s size depends on how much ESR is needed to

prevent the output from dipping too low under a load

transient. Ignoring the sag due to finite capacitance:

In non-CPU applications, the output capacitor’s size

depends on how much ESR is needed to maintain an

acceptable level of output voltage ripple:

Vp p

LIR I

ESR

LOAD MAX

≤

()

ESR

DIP

LOAD MAX

≤

()

kHz A

××

=µµ

300 0 5 7

19 2

. ()HH

f LIR I

OUT

LOAD MAX

××

()

C DUTY V V

SAG

LOAD MAX

F BATT MIN OUT

×× −

()

∆

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P28

MAX1712EEG

Mfr. #:

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Manufacturer:

Maxim Integrated

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LDO Voltage Controllers High-Speed, Digitally Adjusted Step-Down Controllers for Notebook CPUs

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MAX1712EEG

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