©2013 Silicon Storage Technology, Inc. DS-20005014B 11/2013
21
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
Data Sheet
Figure 10:WE# Controlled Block-Erase Timing Diagram
Figure 11:WE# Controlled Sector-Erase Timing Diagram
1297 F09.1
ADDRESS A
19-0
DQ
15-0
WE#
SW0 SW1 SW2 SW3 SW4 SW5
5555 2AAA 2AAA5555 5555
XX55 XX50XX55XXAA XX80 XXAA
BA
X
OE#
CE#
SIX-BYTE CODE FOR BLOCK-ERASE
T
BE
T
WP
Note: This device also supports CE# controlled Block-Erase operation.
The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 17.)
BA
X
= Block Address
WP# must be held in proper logic state (V
IH
) 1 µs prior to and 1 µs after the command sequence.
X can be V
IL
or V
IH,
but no other value.
1297 F10.1
ADDRESS A
19-0
DQ
15-0
WE#
SW0 SW1 SW2 SW3 SW4 SW5
5555 2AAA 2AAA5555 5555
XX55 XX30XX55XXAA XX80 XXAA
SA
X
OE#
CE#
SIX-BYTE CODE FOR SECTOR-ERASE
T
SE
T
WP
Note: This device also supports CE# controlled Sector-Erase operation.
The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 17.)
SA
X
= Sector Address
WP# must be held in proper logic state (V
IH
) 1 µs prior to and 1µs after the command sequence.
X can be V
IL
or V
IH,
but no other value.
