OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

P89LPC952FA,512

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69
P89LPC952_954_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 24 July 2008 10 of 69
NXP Semiconductors
P89LPC952/954
8-bit microcontroller with 10-bit ADC
P0.6/CMP1/
KBI6
34 37 31 I/O P0.6 — Port 0 bit 6.
O CMP1 — Comparator 1 output.
I KBI6 — Keyboard input 6.
P0.7/T1/KBI7 31 35 29 I/O P0.7 — Port 0 bit 7.
I/O T1 — Timer/counter 1 external count input or overflow
output.
I KBI7 — Keyboard input 7.
P1.0 to P1.7 I/O, I
[1]
Port 1: Port 1 is an 8-bit I/O port with a user-configurable
output type, except for three pins as noted below. During
reset Port 1 latches are configured in the input only mode
with the internal pull-up disabled. The operation of the
configurable Port 1 pins as inputs and outputs depends upon
the port configuration selected. Each of the configurable port
pins are programmed independently. Refer to
Section 7.13.1
“Port configurations” and Table 11 “Static characteristics” for
details. P1.2 to P1.3 are open drain when used as outputs.
P1.5 is input only.
All pins have Schmitt triggered inputs.
Port 1 also provides various special functions as described
below:
P1.0/TXD0 4 10 4 I/O P1.0 — Port 1 bit 0.
O TXD0 — Transmitter output for serial port 0.
P1.1/RXD0 3 9 3 I/O P1.1 — Port 1 bit 1.
I RXD0 — Receiver input for serial port 0.
P1.2/T0/SCL 2 8 2 I/O P1.2 — Port 1 bit 2 (open-drain when used as output).
I/O T0 — Timer/counter 0 external count input or overflow
output (open-drain when used as output).
I/O SCL — I
2
C-bus serial clock input/output.
P1.3/
INT0/SDA 1 7 1 I/O P1.3 — Port 1 bit 3 (open-drain when used as output).
I
INT0 — External interrupt 0 input.
I/O SDA — I
2
C-bus serial data input/output.
P1.4/
INT1 48 6 44 I/O P1.4 — Port 1 bit 4.
I
INT1 — External interrupt 1 input.
Table 3. Pin description
…continued
Symbol Pin Type Description
LQFP48 PLCC44 LQFP44
P89LPC952_954_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 24 July 2008 11 of 69
NXP Semiconductors
P89LPC952/954
8-bit microcontroller with 10-bit ADC
P1.5/RST 47 5 43 I P1.5 — Port 1 bit 5 (input only).
I
RST — External Reset input during power-on or maybe a
reset input/output if selected via UCFG1 and UCFG2. When
functioning as a reset input or input/output, a LOW on this
pin resets the microcontroller, causing I/O ports and
peripherals to take on their default states, and the processor
begins execution at address 0. When functioning as a reset
output or input/output an internal reset source will drive this
pin LOW. Also used during a power-on sequence to force
ISP mode. When using an oscillator frequency above
12 MHz, the reset input function of P1.5 must be
enabled. An external circuit is required to hold the
device in reset at power-up until V
DD
has reached its
specified level. When system power is removed V
DD
will
fall below the minimum specified operating voltage.
When using an oscillator frequency above 12 MHz, in
some applications, an external brownout detect circuit
may be required to hold the device in reset when V
DD
falls below the minimum specified operating voltage.
P1.6 46 4 42 I/O P1.6 — Port 1 bit 6.
P1.7/AD04 43 2 40 I/O P1.7 — Port 1 bit 7.
I AD04 — ADC0 channel 4 analog input.
P2.0 to P2.5 I/O Port 2: Port 2 is an 8-bit I/O port with a user-configurable
output type. During reset Port 2 latches are configured in the
input only mode with the internal pull-up disabled. The
operation of Port 2 pins as inputs and outputs depends upon
the port configuration selected. Each port pin is configured
independently. Refer to
Section 7.13.1 “Port configurations”
and
Table 11 “Static characteristics” for details.
All pins have Schmitt triggered inputs.
Port 2 also provides various special functions as described
below:
P2.0/AD07 42 1 39 I/O P2.0 — Port 2 bit 0.
I AD07 — ADC0 channel 7 analog input.
P2.1/AD06 41 44 38 I/O P2.1 — Port 2 bit 1.
I AD06 — ADC0 channel 6 analog input.
P2.2/MOSI 30 34 28 I/O P2.2 — Port 2 bit 2.
I/O MOSI — SPI master out slave in. When configured as
master, this pin is output; when configured as slave, this pin
is input.
P2.3/MISO 29 33 27 I/O P2.3 — Port 2 bit 3.
I/O MISO — When configured as master, this pin is input, when
configured as slave, this pin is output.
P2.4/
SS 28 32 26 I/O P2.4 — Port 2 bit 4.
I/O
SS — SPI Slave select.
Table 3. Pin description
…continued
Symbol Pin Type Description
LQFP48 PLCC44 LQFP44
P89LPC952_954_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 24 July 2008 12 of 69
NXP Semiconductors
P89LPC952/954
8-bit microcontroller with 10-bit ADC
P2.5/SPICLK 27 31 25 I/O P2.5 — Port 2 bit 5.
I/O SPICLK — SPI clock. When configured as master, this pin is
output; when configured as slave, this pin is input.
P2.6 26 - - I/O P2.6 — Port 2 bit 6.
P2.7 5 - - I/O P2.7 — Port 2 bit 7.
P3.0 to P3.1 I/O Port 3: Port 3 is a 2-bit I/O port with a user-configurable
output type. During reset Port 3 latches are configured in the
input only mode with the internal pull-up disabled. The
operation of Port 3 pins as inputs and outputs depends upon
the port configuration selected. Each port pin is configured
independently. Refer to Section 7.13.1 “Port configurations”
and
Table 11 “Static characteristics” for details.
All pins have Schmitt triggered inputs.
Port 3 also provides various special functions as described
below:
P3.0/XTAL2/
CLKOUT
7 12 6 I/O P3.0 — Port 3 bit 0.
O XTAL2 — Output from the oscillator amplifier (when a crystal
oscillator option is selected via the flash configuration.
O CLKOUT — CPU clock divided by 2 when enabled via SFR
bit (ENCLK -TRIM.6). It can be used if the CPU clock is the
internal RC oscillator, watchdog oscillator or external clock
input, except when XTAL1/XTAL2 are used to generate clock
source for the RTC/system timer.
P3.1/XTAL1 6 11 5 I/O P3.1 — Port 3 bit 1.
I XTAL1 — Input to the oscillator circuit and internal clock
generator circuits (when selected via the flash configuration).
It can be a port pin if internal RC oscillator or watchdog
oscillator is used as the CPU clock source, and if
XTAL1/XTAL2 are not used to generate the clock for the
RTC/system timer.
P4.0 to P4.7 I/O Port 4: Port 4 is an 8-bit I/O port with a user-configurable
output type. During reset Port 4 latches are configured in the
input only mode with the internal pull-up disabled. The
operation of Port 4 pins as inputs and outputs depends upon
the port configuration selected. Each port pin is configured
independently. Refer to
Section 7.13.1 “Port configurations”
and
Table 11 “Static characteristics” for details.
All pins have Schmitt triggered inputs.
Port 4 also provides various special functions as described
below:
P4.0 25 30 24 I/O P4.0 — Port 4 bit 0.
P4.1/TRIG 24 29 23 I/O P4.1 — Port 4 bit 1.
O TRIG — Debugger trigger output.
P4.2/TXD1 23 28 22 I/O P4.2 — Port 4 bit 2.
O TXD1 — Transmitter output for serial port 1.
P4.3/RXD1 22 27 21 I/O P4.3 — Port 4 bit 3.
I RXD1 — Receiver input for serial port 1.
Table 3. Pin description
…continued
Symbol Pin Type Description
LQFP48 PLCC44 LQFP44
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69

P89LPC952FA,512

Mfr. #:
Buy P89LPC952FA,512
Manufacturer:
NXP Semiconductors
Description:
Microcontrollers - MCU 8-bit Microcontrollers - MCU 80C51 8K FL 512B RAM
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet