P89LPC952_954_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 24 July 2008 29 of 69
NXP Semiconductors
P89LPC952/954
8-bit microcontroller with 10-bit ADC
7.13 I/O ports
The P89LPC952/954 has six I/O ports: Port 0, Port 1, Port 2, Port 3, Port 4, and Port 5.
Ports 0, 1, 2, 4, and 5 are 8-bit ports, and Port 3 is a 2-bit port. The exact number of I/O
pins available depends upon the clock and reset options and package chosen, as shown
in Table 7.
[1] Required for operation above 12 MHz.
7.13.1 Port configurations
All but three I/O port pins on the P89LPC952/954 may be configured by software to one of
four types on a bit-by-bit basis. These are: quasi-bidirectional (standard 80C51 port
outputs), push-pull, open drain, and input-only. Two configuration registers for each port
select the output type for each port pin.
1. P1.5/RST can only be an input and cannot be configured.
2. P1.2/T0/SCL and P1.3/INT0/SDA may only be configured to be either input-only or
open-drain.
7.13.1.1 Quasi-bidirectional output configuration
Quasi-bidirectional output type can be used as both an input and output without the need
to reconfigure the port. This is possible because when the port outputs a logic HIGH, it is
weakly driven, allowing an external device to pull the pin LOW. When the pin is driven
LOW, it is driven strongly and able to sink a fairly large current. These features are
somewhat similar to an open-drain output except that there are three pull-up transistors in
the quasi-bidirectional output that serve different purposes.
The P89LPC952/954 is a 3 V device, but the pins are 5 V-tolerant. In quasi-bidirectional
mode, if a user applies 5 V on the pin, there will be a current flowing from the pin to V
DD
,
causing extra power consumption. Therefore, applying 5 V in quasi-bidirectional mode is
discouraged.
A quasi-bidirectional port pin has a Schmitt triggered input that also has a glitch
suppression circuit.
7.13.1.2 Open-drain output configuration
The open-drain output configuration turns off all pull-ups and only drives the pull-down
transistor of the port driver when the port latch contains a logic 0. To be used as a logic
output, a port configured in this manner must have an external pull-up, typically a resistor
tied to V
DD
.
Table 7. Number of I/O pins available
Clock source Reset option Number of I/O pins
(48-pin package)
Number of I/O pins
(44-pin package)
On-chip oscillator or watchdog
oscillator
No external reset (except during power-up) 42 40
External
RST pin supported 41 39
External clock input No external reset (except during power-up) 41 39
External
RST pin supported
[1]
40 38
Low/medium/high speed oscillator
(external crystal or resonator)
No external reset (except during power-up) 40 38
External
RST pin supported
[1]
39 37
