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P89LPC952FA,512

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69
P89LPC952_954_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 24 July 2008 25 of 69
NXP Semiconductors
P89LPC952/954
8-bit microcontroller with 10-bit ADC
7.7 CCLK wake-up delay
The P89LPC952/954 has an internal wake-up timer that delays the clock until it stabilizes
depending on the clock source used. If the clock source is any of the three crystal
selections (low, medium and high frequencies) the delay is 992 OSCCLK cycles plus
60 µsto100µs. If the clock source is either the internal RC oscillator, watchdog oscillator,
or external clock, the delay is 224 OSCCLK cycles plus 60 µsto100µs.
7.8 CCLK modification: DIVM register
The OSCCLK frequency can be divided down up to 510 times by configuring a dividing
register, DIVM, to generate CCLK. This feature makes it possible to temporarily run the
CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can
retain the ability to respond to events that would not exit Idle mode by executing its normal
program at a lower rate. This can also allow bypassing the oscillator start-up time in cases
where Power-down mode would otherwise be used. The value of DIVM may be changed
by the program at any time without interrupting code execution.
7.9 Low power select
The P89LPC952/954 is designed to run at 18 MHz (CCLK) maximum. However, if CCLK
is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to ‘1’ to lower the power
consumption further. On any reset, CLKLP is ‘0’ allowing highest performance access.
This bit can then be set in software if CCLK is running at 8 MHz or slower.
Fig 6. Block diagram of oscillator control
÷2
002aab409
RTC
ADC0
CPU
WDT
DIVM
CCLK
OSCCLK
HIGH FREQUENCY
MEDIUM FREQUENCY
LOW FREQUENCY
XTAL1
XTAL2
RC OSCILLATOR
WITH CLOCK DOUBLER
WATCHDOG
OSCILLATOR
(7.3728 MHz/14.7456 MHz ± 1 %)
PCLK
RCCLK
(400 kHz +30 % −20 %)
UARTSI
2
C-BUS
PCLK
TIMER 0 AND
TIMER 1
SPI
RCCLK
P89LPC952_954_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 24 July 2008 26 of 69
NXP Semiconductors
P89LPC952/954
8-bit microcontroller with 10-bit ADC
7.10 Memory organization
The various P89LPC952/954 memory spaces are as follows:
• DATA
128 bytes of internal data memory space (00H:7FH) accessed via direct or indirect
addressing, using instructions other than MOVX and MOVC. All or part of the Stack
may be in this area.
• IDATA
Indirect Data. 256 bytes of internal data memory space (00H:FFH) accessed via
indirect addressing using instructions other than MOVX and MOVC. All or part of the
Stack may be in this area. This area includes the DATA area and the 128 bytes
immediately above it.
• SFR
Special Function Registers. Selected CPU registers and peripheral control and status
registers, accessible only via direct addressing.
• XDATA
‘External’ Data or Auxiliary RAM. Duplicates the classic 80C51 64 kB memory space
addressed via the MOVX instruction using the SPTR, R0, or R1. All or part of this
space could be implemented on-chip. The P89LPC952/954 has 256 bytes of on-chip
XDATA memory, plus extended SFRs located in XDATA.
• CODE
64 kB of Code memory space, accessed as part of program execution and via the
MOVC instruction. The P89LPC952/954 has 8 kB/16 kB of on-chip Code memory.
7.11 Data RAM arrangement
The 768 bytes of on-chip RAM are organized as shown in Table 6.
7.12 Interrupts
The P89LPC952/954 uses a four priority level interrupt structure. This allows great
flexibility in controlling the handling of the many interrupt sources. The P89LPC952/954
supports 17 interrupt sources: external interrupts 0 and 1, timers 0 and 1, serial port 0 TX,
serial port 0 RX, combined serial port 0 RX/TX, serial port 1 TX, serial port 1 RX,
combined serial port 1 RX/TX, brownout detect, watchdog/RTC, I
2
C-bus, keyboard,
comparators 1 and 2, SPI, and ADC completion.
Each interrupt source can be individually enabled or disabled by setting or clearing a bit in
the interrupt enable registers IEN0, IEN1 or IEN2. The IEN0 register also contains a
global disable bit, EA, which disables all interrupts.
Table 6. On-chip data memory usages
Type Data RAM Size (bytes)
DATA Memory that can be addressed directly and indirectly 128
IDATA Memory that can be addressed indirectly 256
XDATA Auxiliary (‘External Data’) on-chip memory that is accessed
using the MOVX instructions
256
P89LPC952_954_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 24 July 2008 27 of 69
NXP Semiconductors
P89LPC952/954
8-bit microcontroller with 10-bit ADC
Each interrupt source can be individually programmed to one of four priority levels by
setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, IP1H, IP2, and
IP2H. An interrupt service routine in progress can be interrupted by a higher priority
interrupt, but not by another interrupt of the same or lower priority. The highest priority
interrupt service cannot be interrupted by any other interrupt source. If two requests of
different priority levels are pending at the start of an instruction, the request of higher
priority level is serviced.
If requests of the same priority level are pending at the start of an instruction, an internal
polling sequence determines which request is serviced. This is called the arbitration
ranking. Note that the arbitration ranking is only used to resolve pending requests of the
same priority level.
7.12.1 External interrupt inputs
The P89LPC952/954 has two external interrupt inputs as well as the Keypad Interrupt
function. The two interrupt inputs are identical to those present on the standard 80C51
microcontrollers.
These external interrupts can be programmed to be level-triggered or edge-triggered by
setting or clearing bit IT1 or IT0 in Register TCON.
In edge-triggered mode, if successive samples of the INTn pin show a HIGH in one cycle
and a LOW in the next cycle, the interrupt request flag IEn in TCON is set, causing an
interrupt request.
If an external interrupt is enabled when the P89LPC952/954 is put into Power-down or Idle
mode, the interrupt will cause the processor to wake-up and resume operation. Refer to
Section 7.15 “Power reduction modes” for details.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69

P89LPC952FA,512

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Buy P89LPC952FA,512
Manufacturer:
NXP Semiconductors
Description:
Microcontrollers - MCU 8-bit Microcontrollers - MCU 80C51 8K FL 512B RAM
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