P89LPC952_954_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 24 July 2008 34 of 69
NXP Semiconductors
P89LPC952/954
8-bit microcontroller with 10-bit ADC
7.17.6 Timer overflow toggle output
Timers 0 and 1 can be configured to automatically toggle a port output whenever a timer
overflow occurs. The same device pins that are used for the T0 and T1 count inputs are
also used for the timer toggle outputs. The port outputs will be a logic 1 prior to the first
timer overflow when this mode is turned on.
7.18 RTC/system timer
The P89LPC952/954 has a simple RTC that allows a user to continue running an accurate
timer while the rest of the device is powered down. The RTC can be a wake-up or an
interrupt source. The RTC is a 23-bit down counter comprised of a 7-bit prescaler and a
16-bit loadable down counter. When it reaches all ‘0’s, the counter will be reloaded again
and the RTCF flag will be set. The clock source for this counter can be either the CPU
clock (CCLK) or the XTAL oscillator, provided that the XTAL oscillator is not being used as
the CPU clock. If the XTAL oscillator is used as the CPU clock, then the RTC will use
CCLK as its clock source. Only power-on reset will reset the RTC and its associated SFRs
to the default state.
7.19 UARTs
The P89LPC952/954 has two enhanced UARTs that are compatible with the conventional
80C51 UART except that Timer 2 overflow cannot be used as a baud rate source. The
P89LPC952/954 does include an independent Baud Rate Generator for each UART
(BRG0 for UART 0 and BRG1 for UART 1). The baud rate can be selected from the
oscillator (divided by a constant), Timer 1 overflow, or the independent Baud Rate
Generator associated with the specific UART. In addition to the baud rate generation,
enhancements over the standard 80C51 UART include Framing Error detection,
automatic address recognition, selectable double buffering and several interrupt options.
The UARTs can be operated in 4 modes: shift register, 8-bit UART, 9-bit UART, and CPU
clock/32 or CPU clock/16.
7.19.1 Mode 0
Serial data enters and exits through RXDn. TXDn outputs the shift clock. 8 bits are
transmitted or received, LSB first. The baud rate is fixed at
1
⁄
16
of the CPU clock
frequency.
7.19.2 Mode 1
10 bits are transmitted (through TXDn) or received (through RXDn): a start bit (logic 0),
8 data bits (LSB first), and a stop bit (logic 1). When data is received, the stop bit is stored
in RB8_n in Special Function Register SnCON. The baud rate is variable and is
determined by the Timer 1 overflow rate or the Baud Rate Generator (described in Section
7.19.5 “Baud rate generator and selection”).
7.19.3 Mode 2
11 bits are transmitted (through TXDn) or received (through RXDn): start bit (logic 0),
8 data bits (LSB first), a programmable 9
th
data bit, and a stop bit (logic 1). When data is
transmitted, the 9
th
data bit (TB8_n in SnCON) can be assigned the value of ‘0’ or ‘1’. Or,
for example, the parity bit (P, in the PSW) could be moved into TB8_n. When data is
received, the 9
th
data bit goes into RB8_n in Special Function Register SnCON, while the
