P89LPC952_954_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 24 July 2008 43 of 69
NXP Semiconductors
P89LPC952/954
8-bit microcontroller with 10-bit ADC
7.25 Additional features
7.25.1 Software reset
The SRST bit in AUXR1 gives software the opportunity to reset the processor completely,
as if an external reset or watchdog reset had occurred. Care should be taken when writing
to AUXR1 to avoid accidental software resets.
7.25.2 Dual data pointers
The dual Data Pointers (DPTR) provides two different Data Pointers to specify the address
used with certain instructions. The DPS bit in the AUXR1 register selects one of the two
Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic 0 so that the DPS bit may
be toggled (thereby switching Data Pointers) simply by incrementing the AUXR1 register,
without the possibility of inadvertently altering other bits in the register.
7.25.3 Debugger interface
This device contains a two-wire serial debugger interface designed to be used with
commercially available debugging tools. An additional trigger output is provided that
maybe triggered using the two-wire debugger interface.
The Freeze register allows the user to selectively disable clocking of peripheral device
timers while in the debugger mode.
The two-wire serial debugger interface can also be used be used to program the code
memory of these devices.
(1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a feed
sequence.
Fig 16. Watchdog timer in Watchdog mode (WDTE = 1)
PRE2 PRE1 PRE0 - - WDRUN WDTOF WDCLK
WDCON (A7H)
SHADOW REGISTER
PRESCALER
002aaa905
8-BIT DOWN
COUNTER
WDL (C1H)
watchdog
oscillator
PCLK
÷32
MOV WFEED1, #0A5H
MOV WFEED2, #05AH
reset
(1)
P89LPC952_954_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 24 July 2008 44 of 69
NXP Semiconductors
P89LPC952/954
8-bit microcontroller with 10-bit ADC
7.26 Flash program memory
7.26.1 General description
The P89LPC952/954 flash memory provides in-circuit electrical erasure and
programming. The flash can be erased, read, and written as bytes. The Sector and Page
Erase functions can erase any flash sector (1 kB) or page (64 bytes). The Chip Erase
operation will erase the entire program memory. ICP using standard commercial
programmers is available. In addition, IAP and byte-erase allows code memory to be used
for non-volatile data storage. On-chip erase and write timing generation contribute to a
user-friendly programming interface. The P89LPC952/954 flash reliably stores memory
contents even after 400,000 erase and program cycles. The cell is designed to optimize
the erase and programming mechanisms. The P89LPC952/954 uses V
DD
as the supply
voltage to perform the Program/Erase algorithms.
7.26.2 Features
Programming and erase over the full operating voltage range.
Byte erase allows code memory to be used for data storage.
Read/Programming/Erase using ISP, IAP, ICP, or two-wire serial debugger.
Internal fixed boot ROM, containing low-level IAP routines available to user code.
Default loader providing ISP via the serial port, located in upper end of user program
memory.
Boot vector allows user-provided flash loader code to reside anywhere in the flash
memory space, providing flexibility to the user.
Any flash program/erase operation in 2 ms.
Programming with industry-standard commercial programmers.
Programmable security for the code in the flash for each sector.
400,000 typical erase/program cycles for each byte.
20 year minimum data retention.
7.26.3 Flash organization
The program memory consists of eight/sixteen 1 kB sectors on the P89LPC952/954
devices. Each sector can be further divided into 64-byte pages. In addition to sector
erase, page erase, and byte erase, a 64-byte page register is included which allows from
1 to 64 bytes of a given page to be programmed at the same time, substantially reducing
overall programming time.
7.26.4 Using flash as data storage
The flash code memory array of this device supports individual byte erasing and
programming. Any byte in the code memory array may be read using the MOVC
instruction, provided that the sector containing the byte has not been secured (a MOVC
instruction is not allowed to read code memory contents of a secured sector). Thus any
byte in a non-secured sector may be used for non-volatile data storage.
P89LPC952_954_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 24 July 2008 45 of 69
NXP Semiconductors
P89LPC952/954
8-bit microcontroller with 10-bit ADC
7.26.5 Flash programming and erasing
Four different methods of erasing or programming of the flash are available. The flash may
be programmed or erased in the end-user application (IAP) under control of the
application’s firmware. Another option is to use the ICP mechanism. This ICP system
provides for programming through a serial clock/serial data interface. As shipped from the
factory, the upper 512 bytes of user code space contains a serial ISP routine allowing for
the device to be programmed in circuit through the serial port. The flash may also be
programmed or erased using a commercially available EPROM programmer which
supports this device. This device does not provide for direct verification of code memory
contents. Instead, this device provides a 32-bit CRC result on either a sector or the entire
user code space.
7.26.6 ICP
ICP is performed without removing the microcontroller from the system. The ICP facility
consists of internal hardware resources to facilitate remote programming of the
P89LPC952/954 through a two-wire serial interface. The Philips ICP facility has made
in-circuit programming in an embedded application—using commercially available
programmers—possible with a minimum of additional expense in components and circuit
board area. The ICP function uses five pins. Only a small connector needs to be available
to interface your application to a commercial programmer in order to use this feature.
Additional details may be found in the P89LPC952/954
User’s Manual
.
7.26.7 IAP
IAP is performed in the application under the control of the microcontroller’s firmware. The
IAP facility consists of internal hardware resources to facilitate programming and erasing.
The Philips IAP has made in-application programming in an embedded application
possible without additional components. Two methods are available to accomplish IAP. A
set of predefined IAP functions are provided in a Boot ROM and can be called through a
common interface, PGM_MTP. Several IAP calls are available for use by an application
program to permit selective erasing and programming of flash sectors, pages, security
bits, configuration bytes, and device ID. These functions are selected by setting up the
microcontroller’s registers before making a call to PGM_MTP at FF03H. The Boot ROM
occupies the program memory space at the top of the address space from FF00H to
FEFFH, thereby not conflicting with the user program memory space.
In addition, IAP operations can be accomplished through the use of four SFRs consisting
of a control/status register, a data register, and two address registers. Additional details
may be found in the P89LPC952/954
User’s Manual
.
7.26.8 ISP
ISP is performed without removing the microcontroller from the system. The ISP facility
consists of a series of internal hardware resources coupled with internal firmware to
facilitate remote programming of the P89LPC952/954 through the serial port. This
firmware is provided by Philips and embedded within each P89LPC952/954 device. The
Philips ISP facility has made in-system programming in an embedded application possible
with a minimum of additional expense in components and circuit board area. The ISP
function uses five pins (V
DD
, V
SS
, TXD, RXD, and RST). Only a small connector needs to
be available to interface your application to an external circuit in order to use this feature.

P89LPC952FA,512

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Microcontrollers - MCU 8-bit Microcontrollers - MCU 80C51 8K FL 512B RAM
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