P89LPC952_954_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 24 July 2008 31 of 69
NXP Semiconductors
P89LPC952/954
8-bit microcontroller with 10-bit ADC
Brownout detection may be enabled or disabled in software.
If brownout detection is enabled the brownout condition occurs when V
DD
falls below the
brownout trip voltage, V
bo
(see Table 11 “Static characteristics”), and is negated when V
DD
rises above V
bo
. If the P89LPC952/954 device is to operate with a power supply that can
be below 2.7 V, BOE should be left in the unprogrammed state so that the device can
operate at 2.4 V, otherwise continuous brownout reset may prevent the device from
operating.
For correct activation of brownout detect, the V
DD
rise and fall times must be observed.
Please see Table 11 “Static characteristics” for specifications.
7.14.2 Power-on detection
The Power-on detect has a function similar to the brownout detect, but is designed to work
as power comes up initially, before the power supply voltage reaches a level where
brownout detect can work. The POF flag in the RSTSRC register is set to indicate an
initial power-up condition. The POF flag will remain set until cleared by software.
7.15 Power reduction modes
The P89LPC952/954 supports three different power reduction modes. These modes are
Idle mode, Power-down mode, and total Power-down mode.
7.15.1 Idle mode
Idle mode leaves peripherals running in order to allow them to activate the processor
when an interrupt is generated. Any enabled interrupt source or reset may terminate Idle
mode.
7.15.2 Power-down mode
The Power-down mode stops the oscillator in order to minimize power consumption. The
P89LPC952/954 exits Power-down mode via any reset, or certain interrupts. In
Power-down mode, the power supply voltage may be reduced to the data retention supply
voltage V
DDR
. This retains the RAM contents at the point where Power-down mode was
entered. SFR contents are not guaranteed after V
DD
has been lowered to V
DDR
, therefore
it is highly recommended to wake-up the processor via reset in this case. V
DD
must be
raised to within the operating range before the Power-down mode is exited.
Some chip functions continue to operate and draw power during Power-down mode,
increasing the total power used during power-down. These include: Brownout detect,
watchdog timer, comparators (note that comparators can be powered down separately),
and RTC/system timer. The internal RC oscillator is disabled unless both the RC oscillator
has been selected as the system clock and the RTC is enabled.
7.15.3 Total Power-down mode
This is the same as Power-down mode except that the brownout detection circuitry and
the voltage comparators are also disabled to conserve additional power. The internal RC
oscillator is disabled unless both the RC oscillator has been selected as the system clock
and the RTC is enabled. If the internal RC oscillator is used to clock the RTC during
power-down, there will be high power consumption. Please use an external low frequency
clock to achieve low power with the RTC running during power-down.
P89LPC952_954_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 24 July 2008 32 of 69
NXP Semiconductors
P89LPC952/954
8-bit microcontroller with 10-bit ADC
7.16 Reset
The P1.5/RST pin can function as either a digital input (P1.5), an active-LOW reset input
with an internal pull-up, a bidirectional reset input/output (open drain output with an
internal pull-up), or as push-pull reset output. These modes are selected by the RPE
(Reset Pin Enable) bit in UCFG1 and the RPE1 (Reset Pin Enable 1) bit in UCFG2.
Remark: During a power-up sequence, the RPE and RPE1 selection is overridden and
this pin always functions as a reset input. An external circuit connected to this pin
should not hold this pin LOW during a power-on sequence as this will keep the
device in reset. After power-up this pin will function as defined by the RPE and RPE1
bits. Only a power-up reset will temporarily override the selection defined by RPE and
RPE1 bits. Other sources of reset will not override the RPE and RPE1 bits.
Remark: During a power cycle, V
DD
must fall below V
POR
before power is reapplied, in
order to ensure a power-on reset (see Table 11 “Static characteristics” on page 51).
Remark: When using an oscillator frequency above 12 MHz, the reset input function of
P1.5 must be enabled. An external circuit is required to hold the device in reset at
power-up until V
DD
has reached its specified level. When system power is removed V
DD
will fall below the minimum specified operating voltage. When using an oscillator
frequency above 12 MHz, in some applications, an external brownout detect circuit may
be required to hold the device in reset when V
DD
falls below the minimum specified
operating voltage.
Reset can be triggered from the following sources:
External reset pin (during power-up or if user configured via UCFG1, UCGF2);
Power-on detect;
Brownout detect;
Watchdog timer;
Software reset;
UART break character detect reset.
For every reset source, there is a flag in the Reset Register, RSTSRC. The user can read
this register to determine the most recent reset source. These flag bits can be cleared in
software by writing a ‘0’ to the corresponding bit. More than one flag bit may be set:
During a power-on reset, both POF and BOF are set but the other flag bits are
cleared.
For any other reset, previously set flag bits that have not been cleared will remain set.
Table 8. Reset pin modes
P1.5/RST mode RPE1 (UCFG2.0) RPE (UCFG1.6)
General purpose input 0 0
Reset input with pull-up 0 1
Bidirectional reset input/output (open drain with pull-up) 1 0
Reset output 1 1
P89LPC952_954_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 24 July 2008 33 of 69
NXP Semiconductors
P89LPC952/954
8-bit microcontroller with 10-bit ADC
7.16.1 Reset vector
Following reset, the P89LPC952/954 will fetch instructions from either address 0000H or
the Boot address. The Boot address is formed by using the boot vector as the high byte of
the address and the low byte of the address = 00H.
The Boot address will be used if a UART break reset occurs, or the non-volatile Boot
Status bit (BOOTSTAT.0) = 1, or the device is forced into ISP mode during power-on (see
P89LPC952/954
User’s Manual
). Otherwise, instructions will be fetched from address
0000H.
7.17 Timers/counters 0 and 1
The P89LPC952/954 has two general purpose counter/timers which are upward
compatible with the standard 80C51 Timer 0 and Timer 1. Both can be configured to
operate either as timers or event counters. An option to automatically toggle the T0 and/or
T1 pins upon timer overflow has been added.
In the ‘Timer’ function, the register is incremented every machine cycle.
In the ‘Counter’ function, the register is incremented in response to a 1-to-0 transition at its
corresponding external input pin, T0 or T1. In this function, the external input is sampled
once during every machine cycle.
Timer 0 and Timer 1 have five operating modes (Modes 0, 1, 2, 3 and 6). Modes 0, 1, 2
and 6 are the same for both Timers/Counters. Mode 3 is different.
7.17.1 Mode 0
Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit
Counter with a divide-by-32 prescaler. In this mode, the Timer register is configured as a
13-bit register. Mode 0 operation is the same for Timer 0 and Timer 1.
7.17.2 Mode 1
Mode 1 is the same as Mode 0, except that all 16 bits of the timer register are used.
7.17.3 Mode 2
Mode 2 configures the Timer register as an 8-bit Counter with automatic reload. Mode 2
operation is the same for Timer 0 and Timer 1.
7.17.4 Mode 3
When Timer 1 is in Mode 3 it is stopped. Timer 0 in Mode 3 forms two separate 8-bit
counters and is provided for applications that require an extra 8-bit timer. When Timer 1 is
in Mode 3 it can still be used by the serial port as a baud rate generator.
7.17.5 Mode 6
In this mode, the corresponding timer can be changed to a PWM with a full period of
256 timer clocks.

P89LPC952FA,512

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Microcontrollers - MCU 8-bit Microcontrollers - MCU 80C51 8K FL 512B RAM
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