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TFA9812HN/N1,518

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66
TFA9812_2 © NXP B.V. 2009. All rights reserved.
Preliminary data sheet Rev. 02 — 22 January 2009 22 of 66
NXP Semiconductors
TFA9812
BTL stereo Class-D audio amplifier with I
2
S input
The I
2
C controls for selecting the +24 dB gain can be found in Section 9.5.6. The GAIN
pin has no function In I
2
C mode.
The TFA9812 features also specific gain settings which are related to < 0.5 %, 10 %, 20 %
or 30 % clipping at the output of the TFA9812. These clipping values are only valid under
the following conditions:
• The volume control is set to 0 dB.
• The gain boost is set to 0 dB.
• A 0 dBFs I
2
S input signal is obtained.
The I
2
C controls for selecting a specific clip level can be found in Section 9.5.6. In Legacy
mode the clip level is set to 10 %.
8.5.6 Output power limiter
Output power can be limited to three discrete levels with respect to the maximum power.
The maximum power output value is determined by the value of the high voltage supply.
Clipping levels (see Section 8.5.5) still apply to the maximum levels of reduced output
voltage swings.
In I
2
C control mode the same output power limiting levels can be selected, see
Section 9.5.6. In Legacy control mode two pins can be used to select the output power
limit level as shown in Table 18.
8.5.7 PWM control for performance improvement
The PWM switching frequency of the TFA9812 is dependent on:
• The sampling frequency, f
s
.
• The sampling frequency setting, f
s
(selected) (see Section 9.5.7).
• The PWM switching frequency setting, f
sw
(selected) (see Section 9.5.6).
Equation 9 shows the relationship between these settings and the PWM carrier
frequency:
(9)
Table 17. GAIN pin functionality
GAIN pin value Function
0 0 dB gain
1 +24 dB gain
Table 18. Legacy mode output power limiter control
Pin value Function
ADSEL2/PLIM2 ADSEL1/PLIM1
0 0 Maximum power
0 1 Maximum power − 1.5 dB
1 0 Maximum power − 3.0 dB
1 1 Maximum power − 4.5 dB
f
sw
f
s
f
s selected)()
----------------------------
f
sw selected()
⋅=
TFA9812_2 © NXP B.V. 2009. All rights reserved.
Preliminary data sheet Rev. 02 — 22 January 2009 23 of 66
NXP Semiconductors
TFA9812
BTL stereo Class-D audio amplifier with I
2
S input
The selected PWM switching frequency is 400 kHz by default and can be set to 350 kHz,
700 kHz and 750 kHz in I
2
C control mode. In Legacy mode 400 kHz is the only option and
this scales linearly if 32 kHz or 48 kHz is used as f
s
.
Remark: The selected sample frequency, f
s
(selected) must be equal to the sample
frequency (f
s
) in I
2
C control mode.
Remark: The performance of AM radio reception can sometimes be improved by
selecting non-interfering frequencies for the PWM signal.
8.6 Class-D amplification
The Class-D power amplification of the PWM signal is carried out in two BTL power
stages. The output signal voltage level is determined by the values on the V
DDP
pins.
The power amplifiers can be explicitly put into 3-state mode by using the pin ENABLE as
shown in Table 19. The ENABLE pin is functional in Legacy mode and in I
2
C mode.
[1] Can be overruled by a forced 3-state in Sleep or Fault mode.
8.7 Protection mechanisms
The TFA9812 has a wide range of protection mechanisms to facilitate optimal and safe
application. All of these are active in both I
2
C and Legacy control modes.
The following protections are included in the TFA9812:
• Thermal Foldback (TF)
• OverTemperature Protection (OTP)
• OverCurrent Protection (OCP)
• OverVoltage Protection (OVP)
• UnderVoltage Protection (UVP)
• Window Protection (WP)
• Lock Protection (LP)
• UnderFrequency Protection (UFP)
• OverFrequency Protection (OFP)
• Invalid BCK Protection (IBP)
• DC-blocking
• ESD
The reaction of the device to the different fault conditions differs per protection.
Table 19. ENABLE pin functionality
ENABLE pin value Function
0 Output stages in 3-state mode.
1 Switching enabled
[1]
.
TFA9812_2 © NXP B.V. 2009. All rights reserved.
Preliminary data sheet Rev. 02 — 22 January 2009 24 of 66
NXP Semiconductors
TFA9812
BTL stereo Class-D audio amplifier with I
2
S input
8.7.1 Thermal foldback
If the junction temperature of the TFA9812 exceeds the programmable Thermal foldback
threshold temperature the gain of the amplifier is decreased gradually to a level where the
combination of dissipation (P) and the thermal resistance from junction to ambient (R
th(j-a)
)
results in a junction temperature around the threshold temperature.
This means that the device will not completely switch off, but remains operational at lower
output power levels. Especially with music output signals this feature enables high peak
output power while still operating without any external heat sink other than the
printed-circuit board area. If the junction temperature still increases due to external
causes, the OTP switches the amplifier to 3-state mode.
Under I
2
C control the Thermal foldback threshold temperature value can be lowered
(see Section 9.5.8): In Legacy control mode the default threshold value of 125 °C is fixed.
8.7.2 Overtemperature protection
This is a ‘hard’ protection to prevent heat damage to the TFA9812. The overtemperature
threshold level is the 160 °C junction temperature.
When the threshold temperature is exceeded the output stages are set to 3-state mode.
The temperature is then checked at 1 µs intervals and the output stages will operate
normally again once the temperature has dropped below the threshold level.
OTP is flagged by a low DIAG pin. The TFA9812 temperature is an I
2
C reading, see
Section 9.5.9.
Under normal conditions thermal foldback prevents the overtemperature protection from
being triggered.
8.7.3 Overcurrent protection
The output current of the power amplifiers is current-limited. When an output stage
exceeds a current of 3 A typical, the output stages are set to 3-state mode and after 1 µs
the stages will start operating normally again. These interruptions are not audible.
OCP is flagged by a low DIAG pin and by a high DIAG I
2
C status bit, see Section 9.5.10.
I
2
C settings remain valid.
8.7.4 Overvoltage protection
The supply for the power stages (V
DDA
, V
DDP
) is protected against overvoltage. When a
supply voltage exceeds 20 V the device will enter Sleep mode. When the supply voltage
has fallen below 20 V again the power-up sequence is started.
OVP is flagged by a low DIAG pin and by a high DIAG I
2
C status bit, see Section 9.5.10.
I
2
C settings remain valid.
8.7.5 Undervoltage protections
The supplies are protected against undervoltage. When this is detected the device will
enter Sleep mode. When the supply voltage has risen to a sufficient level again the
power-up sequence is started.
Table 20 shows the UVP trigger levels for the V
DDA
and V
DDA(3V3)
supplies:
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66

TFA9812HN/N1,518

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NXP Semiconductors
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IC AMP AUDIO 15W STER D 48HVQFN
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