OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

TFA9812HN/N1,518

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66
TFA9812_2 © NXP B.V. 2009. All rights reserved.
Preliminary data sheet Rev. 02 — 22 January 2009 43 of 66
NXP Semiconductors
TFA9812
BTL stereo Class-D audio amplifier with I
2
S input
[1] V
ss
= V
SS1
= V
SS2
= REFA = REFD
12. Thermal characteristics
[1] Measured in a JEDEC high K-factor test board (standard EIA/JESD 51-7).
[2] Measured in free air with natural convection.
[3] Strongly depends on where measurement is made on the case: worst-case value stated.
V
x
voltage on pin x DIAG
[1]
V
SS
− 0.3 V
SS
+ 12 V
POWERUP
[1]
V
SS
− 0.3 V
DDA
+ 0.3 V
ENABLE, GAIN, CSEL,
ADSEL2/PLIM2,
ADSEL2/PLIM1,SCL/SFOR,
SDA/MS, DATA, WS, BCK,
MCLK
[1]
V
SS
− 0.5 V
SS
+ 5.5 V
AVOL
[1]
V
SS
− 0.5 V
SS
+ 4.6 V
V
esd
electrostatic discharge voltage according to the human body model
STAB1 and STAB2 with
respect to other pins
−1750 +1750 V
all other pins −2+2 kV
according to the charge
device model
−500 +500 V
Table 53. Limiting values
…continued
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
Table 54. Thermal Characteristics
Symbol Parameter Condition Min Typ Max Unit
R
th(j-a)
thermal resistance
from junction to
ambient
No air flow, JEDEC board
[1][2]
- - 42 K/W
No air flow; typical 4L board in
the NXP 4L reference
application
[2]
- - 36 K/W
No air flow; typical 2L board in
the NXP 2L reference
application
[2]
- - 42 K/W
R
th(j-c)
thermal resistance
from junction to case
[3]
5 - - K/W
R
th(j-lead)
thermal resistance
from junction to lead
Worst-case pin 5 - - K/W
TFA9812_2 © NXP B.V. 2009. All rights reserved.
Preliminary data sheet Rev. 02 — 22 January 2009 44 of 66
NXP Semiconductors
TFA9812
BTL stereo Class-D audio amplifier with I
2
S input
13. Characteristics
13.1 DC Characteristics
Table 55. DC characteristics
Unless specified otherwise, V
DDA
=V
DDP
= 12 V, V
SSP1
= V
SSP2
= 0 V, V
DDA(3V3)
=V
DDD(3V3)
= 3.3 V,
V
SS1
=V
SS2
= REFD = REFA = 0 V, T
amb
=25
°
C, R
L
=8
Ω
, f
i
= 1 kHz, f
s
= 44.1 kHz, f
sw
= 400 kHz, 24-bit I
2
S input data,
MCLK clock mode, typical application diagram (
Figure 13).
Symbol Parameter Condition Min Typ Max Unit
Supply voltage
V
DDA
analog supply
voltage
81220V
V
DDP
power supply voltage 8 12 20 V
V
DDA(3V3)
analog supply
voltage (3.3 V)
3.0 3.3 3.6 V
V
DDD(3V3)
digital supply voltage
(3.3 V)
3.0 3.3 3.6 V
I
P
supply current soft mute mode, with
load, filter and snubbers
connected
[1]
-3845mA
sleep mode
[1]
- 160 270 µA
I
DDA(3V3)
analog supply
current (3.3 V)
operating mode
I
2
S slave mode - 2 4 mA
I
2
S master mode - 4 6 mA
sleep mode
V
DDA
=V
DDP
=12V - 120 - µA
V
DDA
=V
DDP
=1V - 40 70 µA
I
DDD(3V3)
digital supply current
(3.3 V)
operating mode
I
2
S slave mode - 15 25 mA
I
2
S master mode - 25 40 mA
sleep mode;
DATA=WS=BCK=
MLCK = 0 V
-430µA
Amplifier output pins; pins OUT1P, OUT1N, OUT2P and OUT2N
|V
O(offset)
| output offset voltage soft mute mode - - 5 mV
Power-up pin
V
IH
HIGH-level input
voltage
With respect to V
SS1
2.1 - V
DDD(3V3)
V
V
IL
LOW-level input
voltage
With respect to V
SS1
−0.3 - +0.8 V
I
I
input current - 0.1 20 µA
MCLK, BCK, WS, DATA pin
V
IH
HIGH-level input
voltage
With respect to V
SS2
0.7 × V
DDD(3V3)
-- V
V
IL
LOW-level input
voltage
With respect to V
SS2
- - 0.3 × V
DDD(3V3)
V
C
i
input capacitance - - 3 pF
TFA9812_2 © NXP B.V. 2009. All rights reserved.
Preliminary data sheet Rev. 02 — 22 January 2009 45 of 66
NXP Semiconductors
TFA9812
BTL stereo Class-D audio amplifier with I
2
S input
V
OH
HIGH-level output
voltage
At I
OH
= −0.4 mA V
DDD(3V3)
− 0.4 V - - V
V
OL
LOW-level output
voltage
At I
OL
= 4 mA - - 400 mV
C
L
load capacitance - - 50 pF
SDA/MS, SCL/SFOR pin
V
IH
HIGH-level input
voltage
With respect to V
SS2
0.7 × V
DDD(3V3)
- 5.5 V
V
IL
LOW-level input
voltage
With respect to V
SS2
−0.3 - 0.3 × V
DDD(3V3)
V
V
hys(i)
input hysteresis
voltage
With respect to V
SS2
0.1 × V
DDD(3V3)
-- V
C
i
input capacitance - - 2.5 pF
V
OL
LOW-level output
voltage
At I
OL
= 3 mA - - 400 mV
ENABLE, GAIN, CSEL, ADSEL2/PLIM2, ASEL1/PLIM1 pin
V
IH
HIGH-level input
voltage
With respect to V
SS2
0.7 × V
DDD(3V3)
-- V
V
IL
LOW-level input
voltage
With respect to V
SS2
- 0.3 × V
DDD(3V3)
V
V
hys(i)
input hysteresis
voltage
With respect to V
SS2
0.1 × V
DDD(3V3)
-- V
I
I
input current - 50 93 µA
Regulators
V
o
output voltage STAB1 − V
SS1
10 11 12 V
STAB2 − V
SS1
10 11 12 V
STABA − REFA 1.65 1.8 1.95 V
STABD − REFD 1.65 1.8 1.95 V
CDELAY pin
V
CDELAY
voltage on pin
CDELAY
Relative to positive
analog power supply
-V
DDA
−1- V
Crystal pins
V
o(xtal)(p-p)
peak-to-peak crystal
oscillator output
voltage
With respect to V
SS2
- 1.8 - V
AVOL pin
V
i
input voltage Mute level, with respect
to V
SS2
0.77 0.8 0.83 V
0 dB level with respect
to V
SS2
2.74 2.8 2.86 V
I
I
input current - - 1 µA
Table 55. DC characteristics
…continued
Unless specified otherwise, V
DDA
=V
DDP
= 12 V, V
SSP1
= V
SSP2
= 0 V, V
DDA(3V3)
=V
DDD(3V3)
= 3.3 V,
V
SS1
=V
SS2
= REFD = REFA = 0 V, T
amb
=25
°
C, R
L
=8
Ω
, f
i
= 1 kHz, f
s
= 44.1 kHz, f
sw
= 400 kHz, 24-bit I
2
S input data,
MCLK clock mode, typical application diagram (
Figure 13).
Symbol Parameter Condition Min Typ Max Unit
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66

TFA9812HN/N1,518

Mfr. #:
Buy TFA9812HN/N1,518
Manufacturer:
NXP Semiconductors
Description:
IC AMP AUDIO 15W STER D 48HVQFN
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet