TFA9812_2 © NXP B.V. 2009. All rights reserved.
Preliminary data sheet Rev. 02 — 22 January 2009 31 of 66
NXP Semiconductors
TFA9812
BTL stereo Class-D audio amplifier with I
2
S input
9.5.1 Interpolator settings and soft mute
9.5.2 Volume control
Table 28. Register address 00h: miscellaneous I
2
C interpolator settings
Bit 15 14 13 12 11 10 9 8
Symbol RSD RSD RSD RSD RSD RSD RSD RSD
Default 00000000
Bit 7 6 5 4 3 2 1 0
Symbol RSD INV_POL ROFF1 ROFF0 FDEMP2 FDEMP1 FDEMP0 S_MUTE
Default 00100001/0
Table 29. Bit description of register 00h: miscellaneous I
2
C interpolator settings
Bit Symbol Description
6 INV_POL Enable polarity inversion:
0 = No polarity inversion (left audio signal connected to
channel 1; right signal to channel 2)
1 = Polarity inversion enabled
5 to 4 ROFF[1:0] Filter roll-off sharpness:
0 = Slow filter roll-off (2 to 8 f
s
) stop band > 0.7619 f
s
1 = Slow filter roll-off (2 to 8 f
s
) stop band > 0.7619 f
s
2 = Fast filter roll-off (2 to 8 f
s
) stop band > 0.6094 f
s
3 = Fast filter roll-off (2 to 8 f
s
) stop band > 0.6094 f
s
3 to 1 FDEMP[2:0] Digital de-emphasis setting:
0 = No digital de-emphasis
1 = Digital de-emphasis for f
s
= 32 kHz
2 = Digital de-emphasis for f
s
= 44.1 kHz
3 = Digital de-emphasis for f
s
= 48 kHz
4 = Digital de-emphasis for f
s
= 96 kHz
5 to 8 = No digital de-emphasis
0 S_MUTE Soft mute:
0 = Soft mute disabled using raised cosine (default in
Legacy control mode)
1 = Soft mute enabled using raised cosine (default in
I
2
C control mode)
Table 30. Register address 01h: volume control
Bit 15 14 13 12 11 10 9 8
Symbol VOL_L7 VOL_L6 VOL_L5 VOL_L4 VOL_L3 VOL_L2 VOL_L1 VOL_L0
Default 00000000
Bit 7 6 5 4 3 2 1 0
Symbol VOL_R7 VOL_R6 VOL_R5 VOL_R4 VOL_R3 VOL_R2 VOL_R1 VOL_R0
Default 00000000
TFA9812_2 © NXP B.V. 2009. All rights reserved.
Preliminary data sheet Rev. 02 — 22 January 2009 32 of 66
NXP Semiconductors
TFA9812
BTL stereo Class-D audio amplifier with I
2
S input
9.5.3 Digital input format
9.5.4 Equalizer configuration
Table 31. Bit description of register 00h: miscellaneous I
2
C interpolator settings
Bit Symbol Description
15 to 8 VOL_L[15:8] See
Table 16 for suppression levels on left channel as
function of data byte setting.
7 to 0 VOL_R[7:0] See
Table 16 for suppression levels on right channel as
function of data byte setting.
Table 32. Register address 02h: digital input format
Bit 15 14 13 12 11 10 9 8
Symbol RSD RSD RSD RSD RSD RSD RSD RSD
Default 00000000
Bit 7 6 5 4 3 2 1 0
Symbol RSD RSD RSD RSD DI_FOR2 DI_FOR1 DI_FOR0 WS_POL
Default 00000110
Table 33. Bit description of register 02h: digital input format
Bit Symbol Description
3 to 1 DI_FOR[2:0] Digital audio input format:
0 = RSD
1 = RSD
2 = MSB-justified data up to 24 bits
3 = I
2
S data up to 24 bits
4 = LSB-justified 16-bit data
5 = LSB-justified 18-bit data
6 = LSB-justified 20-bit data
7 = LSB-justified 24-bit data
0 WS_POL Enable WS signal polarity inversion:
0 = No WS signal polarity inversion
1 = WS signal polarity inversion enabled
Table 34. Register address 03h: equalizer configuration
Bit 15 14 13 12 11 10 9 8
Symbol RSD RSD RSD RSD RSD RSD RSD RSD
Default 00000000
Bit 7 6 5 4 3 2 1 0
Symbol RSD RSD RSD RSD RSD RSD EQ_BP EQ_BND
Default 00000010
TFA9812_2 © NXP B.V. 2009. All rights reserved.
Preliminary data sheet Rev. 02 — 22 January 2009 33 of 66
NXP Semiconductors
TFA9812
BTL stereo Class-D audio amplifier with I
2
S input
9.5.5 Equalizer settings
[1] Default settings are shown in Table 27. The corresponding equalizer configuration is shown in Table 40.
[1] Default settings are shown in Table 27. The corresponding equalizer configuration is shown in Table 40.
Table 35. Bit description of register 03h: equalizer configuration
Bit Symbol Description
1 EQ_BP Equalizer bypass enable:
0 = Equalizer not bypassed
1 = Equalizer bypassed
0 EQ_BND Equalizer 10-band or 5-band configuration selection:
0 = 10-band equalizer configuration enabled
1 = 5-band equalizer configuration enabled
Table 36. Register addresses xxh = 04, 06...2A
For word1 for equalizer 'yy' see Figure 9
Bit 15 14 13 12 11 10 9 8
Symbol Eyy_t
1
Eyy_k
1m
10 Eyy_k
1m
9 Eyy_k
1m
8 Eyy_k
1m
7 Eyy_k
1m
6 Eyy_k
1m
5 Eyy_k
1m
4
Default
[1]
--------
Bit 7 6 5 4 3 2 1 0
Symbol Eyy_k
1m
3 Eyy_k
1m
2 Eyy_k
1m
1 Eyy_k
1m
0 Eyy_k
1e
3 Eyy_k
1e
2 Eyy_k
1e
1 Eyy_k
1e
0
Default
[1]
--------
Table 37. Register addresses xxh = 05, 07...2B
For word2 for equalizer 'yy' see Figure 9
Bit 15 14 13 12 11 10 9 8
Symbol Eyy_t
2
Eyy_k
2m
3 Eyy_k
2m
2 Eyy_k
2m
1 Eyy_k
2m
0 Eyy_k
2e
2 Eyy_k
2e
1 Eyy_k
2e
0
Default --------
Bit 7 6 5 4 3 2 1 0
Symbol Eyy_k
0
6 Eyy_k
0
5 Eyy_k
0
4 Eyy_k
0
3 Eyy_k
0
2 Eyy_k
0
1 Eyy_k
0
0 Eyy_s
Default --------

TFA9812HN/N1,518

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC AMP AUDIO 15W STER D 48HVQFN
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet