TFA9812HN/N1,518 Datasheet TFA9812HN/N1,518, TFA9812HN/N1,557 | P25-P27

Preliminary data sheet Rev. 02 — 22 January 2009 25 of 66

NXP Semiconductors

TFA9812

BTL stereo Class-D audio ampliﬁer with I

S input

8.7.6 Overdissipation protection

When the output current of the power ampliﬁers exceeds a current value of 3 A and the

temperature is above 140 °C, overdissipation protection is activated and the device enters

Sleep mode. A restart will be initiated automatically when the two overdissipation

conditions are both changed to ‘false’.

Overdissipation is ﬂagged by a low DIAG pin and by a high DIAG I

C status bit, see

Section 9.5.10.

Under normal conditions thermal foldback prevents overdissipation protection from being

triggered. I

C settings remain valid.

8.7.7 Window protection

Window protection is a feature for protecting the device against shorts from the outputs to

the ground or supply lines. If during power-up one of the outputs is shorted to V

SSPx

DDP

, power-up does not proceed any further. The trigger levels for these conditions are:

• OUTxx > V

DDA

− 1 V, or

• OUTxx < REFA + 1 V.

The WP alarm is ﬂagged by a low DIAG pin and by a high DIAG I

C status bit, see

Section 9.5.10.

8.7.8 Lock protection

When the selected clock input source (MCLK, BCK or crystal) stops running, the TFA9812

is able to detect this and set the output stages to 3-state mode. Without this protection

peripheral devices in an application might be damaged.

The PLL lock indication is an I

C reading and will be ‘false’ in the event of a clock

interruption, see Section 9.5.10.

8.7.9 Underfrequency protection

UFP sets the output stages to 3-state mode when the clock input source is too low. The

PWM switching frequency can becomes critically low when the clock input source is lower

than speciﬁed. Without UFP peripheral devices in an application might be damaged.

The status of the UFP is shown in I

C reading register, see Section 9.5.10.

8.7.10 Overfrequency protection

OFP sets the output stages to 3-state mode when the clock input source is too high. The

PWM controller can become unstable when the clock input source is higher than

speciﬁed. Without OFP peripheral devices in an application might be damaged.

The status of the OFP is shown in I

C reading register, see Section 9.5.10.

Table 20. Undervoltage trigger levels

Pin name UVP level DIAG pin (protection active)

Min Max

DDA

≥ 7 V < 8 V LOW

DDA(3V3)

≥ 1.6 V < 3 V -

Preliminary data sheet Rev. 02 — 22 January 2009 26 of 66

NXP Semiconductors

TFA9812

BTL stereo Class-D audio ampliﬁer with I

S input

8.7.11 Invalid BCK protection

The BCK clock signal is veriﬁed as being at one of the allowed relative frequencies: 32 f

48 f

or 64 f

. If it is not at one of these frequencies the TFA9812 will set the output stages

to 3-state mode to prevent audible effects.

The MCLK clock signal is also veriﬁed as being valid, see Section 8.2.3.

Detection of violation results in an automatic internal overruling of the MCLK assignment

to BCK.

8.7.12 DC blocking

The TFA9812 features a high pass ﬁlter after the I

S input to block DC signals. DC values

at the output can damage the peripheral devices. The high pass ﬁlter is always enabled.

8.7.13 Overview protections

Table 21 shows the overview of the protections.

Table 21. Overview protections

Protections

Symbol Conditions DIAG

ﬂag

[1]

Output Recovering

TF programmable

max. T

> 125 °C

Floating - Switching Automatic, increasing

volume control back to

volume setting

OTP T

> 160 °C LOW DIAG Floating Automatic, after 1 µs and

< 160 °C

OCP I

> I

ORM

LOW DIAG Floating Automatic, after 1 µs and

ORM

OVP V

DDA

> 20 V LOW DIAG Floating Restart (fault to operating

when V

DDA

> 8 V and

DDA(3V3)

>3V)

UVP V

DDA

< 8 V or

DDA(3V3)

<3V

LOW DIAG Floating Restart (fault to operating

when V

DDA

> 8 V and

DDA(3V3)

>3V)

ODP T

> 140 °C and I

ORM

LOW DIAG Floating Restart (fault to operating

when T

< 140 °C or

IO < I

ORM

)

[2]

OUTX > V

DDA

− 1 V or

OUTX < REFA + 1 V

LOW DIAG Floating Restart (fault to operating

when OUTX < V

DDA

− 1V

and OUTX > V

SSA

+1V)

LP PLL out of lock Floating LP Floating Restart (fault to operating

when PLL is in lock)

UFP PLL frequency < 45 MHz Floating UFP Floating Restart (fault to operating

when

PLL frequency > 45 MHz)

Preliminary data sheet Rev. 02 — 22 January 2009 27 of 66

NXP Semiconductors

TFA9812

BTL stereo Class-D audio ampliﬁer with I

S input

[1] See, Section 9.5.10.

[2] Window Protection is only checked at power-up.

9. I

C bus interface and register settings

9.1 I

C bus interface

The TFA9812 supports the 400 kHz I

C bus microcontroller interface mode standard. This

can be used to control the TFA9812 and to exchange data with it when in I

C control

mode, see Section 8.2.1.

The TFA9812 can operate in I

C slave mode only as slave receiver or a slave transmitter.

The serial hardware interface involves the pins of the TFA9812 as described in Table 22.

Voltage values applied to the I

C bus device address pins are interpreted as described in

Table 23.

9.2 I

C bus TFA9812 device addresses

Table 24 shows the register address options for the TFA9812 as part of the 8-bit byte that

contains the device address as well as the bit indicator read/write_not R/!W. The TFA9812

supports four different addresses, each of which can be conﬁgured using the pins

ADSEL1/PLIM1 and ADSEL2/PLIM2, see Table 22.

OFP PLL frequency > 140 MHz Floating OFP Floating Restart (fault to operating

when

PLL frequency < 140 MHz)

IBP BCK/WS is not 32 ± 2,

48 2 or 64 2

Floating - Floating Restart (fault to operating

when BCK/WS is 32 ± 2,

48 2 or 64 2)

Table 21. Overview protections

…continued

Protections

Symbol Conditions DIAG

ﬂag

[1]

Output Recovering

Table 22. I

C pins in I

C control mode

Pin name Description

SCL/SFOR I

C bus clock input

SDA/MS I

C bus data input and output

ADSEL2/PLIM2 I

C bus device address bit A2

ADSEL1/PLIM1 I

C bus device address bit A1

Table 23. I

C pin voltages in I

C control mode

Logic value Voltage A2/A1

0< V

1> V

Table 24. I

C bus device address

(MSB) Bit (LSB)

11010A2A1R/!W

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48 P49-P51 P52-P54 P55-P57 P58-P60 P61-P63 P64-P66

TFA9812HN/N1,518

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IC AMP AUDIO 15W STER D 48HVQFN

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TFA9812HN/N1,518

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