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ADC1415S125/DB,598

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42
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ADC1415S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 4 — 17 December 2010 10 of 42
NXP Semiconductors
ADC1415S series
Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs
10. Dynamic characteristics
10.1 Dynamic characteristics
Table 7. Dynamic characteristics
[1]
Symbol Parameter Conditions ADC1415S065 ADC1415S080 ADC1415S105 ADC1415S125 Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
Analog signal processing
α
2H
second
harmonic level
f
i
=3MHz -87--87--86--88-dBc
f
i
=30MHz -86--86--86--87-dBc
f
i
=70MHz -85--85--84--85-dBc
f
i
=170MHz -82--82--81--83-dBc
α
3H
third harmonic
level
f
i
=3MHz -86--86--85--87-dBc
f
i
=30MHz -85--85--85--86-dBc
f
i
=70MHz -84--84--83--84-dBc
f
i
=170MHz -81--81--80--82-dBc
THD total harmonic
distortion
f
i
=3MHz -83--83--82--84-dBc
f
i
=30MHz -82--82--82--83-dBc
f
i
=70MHz -81--81--80--81-dBc
f
i
=170MHz -78--78--77--79-dBc
ENOB effective
number of bits
f
i
= 3 MHz - 11.7 - - 11.7 - - 11.6 - - 11.6 - bits
f
i
= 30 MHz - 11.6 - - 11.5 - - 11.5 - - 11.5 - bits
f
i
= 70 MHz - 11.5 - - 11.5 - - 11.4 - - 11.4 - bits
f
i
= 170 MHz - 11.4 - - 11.4 - - 11.3 - - 11.3 - bits
SNR signal-to-
noise ratio
f
i
= 3 MHz - 72.1 - - 72.0 - - 71.8 - - 71.4 - dBFS
f
i
= 30 MHz - 71.3 - - 71.2 - - 71.2 - - 71.1 - dBFS
f
i
= 70 MHz - 70.7 - - 70.7 - - 70.6 - - 70.5 - dBFS
f
i
= 170 MHz - 70.2 - - 70.1 - - 70.0 - - 69.9 - dBFS
SFDR spurious-
free dynamic
range
f
i
=3MHz -86--86--85--87-dBc
f
i
=30MHz -85--85--85--86-dBc
f
i
=70MHz -84--84--83--84-dBc
f
i
=170MHz -81--81--80--82-dBc
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
ADC1415S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 4 — 17 December 2010 11 of 42
NXP Semiconductors
ADC1415S series
Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs
[1] Typical values measured at V
DDA(3V)
=3V, V
DDO
= 1.8 V, V
DDA(5V)
=5V; T
amb
=25°C and C
L
= 5 pF; minimum and maximum values are across the full temperature range
T
amb
= −40 °C to +85 °C at V
DDA(3V)
=3V, V
DDO
=1.8V, V
DDA(5V)
=5V, V
INP
− V
INM
= −1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise
specified.
IMD Intermodul-
ation distortion
f
i
=3MHz -89--89--88--89-dBc
f
i
=30MHz -88--88--88--88-dBc
f
i
=70MHz -87--87--86--86-dBc
f
i
=170MHz -84--85--83--84-dBc
Table 7. Dynamic characteristics
[1]
…continued
Symbol Parameter Conditions ADC1415S065 ADC1415S080 ADC1415S105 ADC1415S125 Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
ADC1415S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 4 — 17 December 2010 12 of 42
NXP Semiconductors
ADC1415S series
Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs
10.2 Clock and digital output timing
Table 8. Clock and digital output timing characteristics
[1]
Symbol Parameter Conditions ADC1410S065 ADC1410S080 ADC1410S105 ADC1410S125 Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
Clock timing input: pins CLKP and CLKM
f
clk
clock frequency 40 - 65 60 - 80 75 - 105 100 - 125 MHz
t
lat(data)
data latency
time
- 13.5 - - 13.5 - - 13.5 - - 13.5 - clock
cycles
δ
clk
clock duty cycle DCS_EN = 1 30 50 70 30 50 70 30 50 70 30 50 70 %
DCS_EN=0 455055455055455055455055%
t
d(s)
sampling delay
time
-0.8--0.8--0.8--0.8-ns
t
wake
wake-up time -76--76--76--76-μs
CMOS Mode timing output: pins D13 to D0 and DAV
t
PD
propagation
delay
DATA 13.6 14.9 16.4 11.9 12.9 14.4 8.0 10.8 12.4 8.2 9.7 11.3 ns
DAV -4.2--3.6--3.3--3.4-ns
t
su
set-up time - 12.5 - - 9.8 - - 6.8 - - 5.6 - ns
t
h
hold time -3.4--3.3--3.1--2.8-ns
t
r
rise time DATA
[2]
0.39 - 2.4 0.39 - 2.4 0.39 - 2.4 0.39 - 2.4 ns
DAV 0.26 - 2.4 0.26 - 2.4 0.26 - 2.4 0.26 - 2.4 ns
t
f
fall time DATA
[2]
0.19 - 2.4 0.19 - 2.4 0.19 - 2.4 0.19 - 2.4 ns
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42

ADC1415S125/DB,598

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Buy ADC1415S125/DB,598
Manufacturer:
NXP Semiconductors
Description:
BOARD DEMO FOR ADC1415S125
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