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ADC1415S125/DB,598

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42
ADC1415S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 4 — 17 December 2010 28 of 42
NXP Semiconductors
ADC1415S series
Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs
11.5.7 Output codes versus input voltage
11.6 Serial Peripheral Interface (SPI)
11.6.1 Register description
The ADC1415S serial interface is a synchronous serial communications port that allows
easy interfacing with many commonly-used microprocessors. It provides access to the
registers that control the operation of the chip.
This interface is configured as a 3-wire type (SDIO as bidirectional pin)
Pin SCLK is the serial clock input and CS
is the chip select pin.
Each read/write operation is initiated by a LOW level on CS. A minimum of three bytes is
transmitted (two instruction bytes and at least one data byte). The number of data bytes is
determined by the value of bits W1 and W2 (see Table 17
).
[1] Bit R/W indicates whether it is a read (logic 1) or a write (logic 0) operation.
[2] Bits W1 and W0 indicate the number of bytes to be transferred after the instruction byte (see Table 17
).
Table 15. Output codes
V
INP
− V
INM
Offset binary Two’s complement OTR pin
< −1 00 0000 0000 0000 10 0000 0000 0000 1
−1 00 0000 0000 0000 10 0000 0000 0000 0
−0.9998779 00 0000 0000 0001 10 0000 0000 0001 0
−0.9997559 00 0000 0000 0010 10 0000 0000 0010 0
−0.9996338 00 0000 0000 0011 10 0000 0000 0011 0
−0.9995117 00 0000 0000 0100 10 0000 0000 0100 0
.... .... .... 0
−0.0002441 01 1111 1111 1110 11 1111 1111 1110 0
−0.0001221 01 1111 1111 1111 11 1111 1111 1111 0
0 10 0000 0000 0000 00 0000 0000 0000 0
+0.0001221 10 0000 0000 0001 00 0000 0000 0001 0
+0.0002441 10 0000 0000 0010 00 0000 0000 0010 0
.... .... .... 0
+0.9995117 11 1111 1111 1011 01 1111 1111 1011 0
+0.9996338 11 1111 1111 1100 01 1111 1111 1100 0
+0.9997559 11 1111 1111 1101 01 1111 1111 1101 0
+0.9998779 11 1111 1111 1110 01 1111 1111 1110 0
+1 11 1111 1111 1111 01 1111 1111 1111 0
> +1 11 1111 1111 1111 01 1111 1111 1111 1
Table 16. Instruction bytes for the SPI
MSB LSB
Bit 76543210
Description R/W
[1]
W1
[2]
W0
[2]
A12 A11 A10 A9 A8
A7 A6 A5 A4 A3 A2 A1 A0
ADC1415S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 4 — 17 December 2010 29 of 42
NXP Semiconductors
ADC1415S series
Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs
Bits A12 to A0 indicate the address of the register being accessed. In the case of a
multiple byte transfer, this address is the first register to be accessed. An address counter
is increased to access subsequent addresses.
The steps involved in a data transfer are as follows:
1. A falling edge on CS
in combination with a rising edge on SCLK determine the start of
communications.
2. The first phase is the transfer of the 2-byte instruction.
3. The second phase is the transfer of the data which can vary in length but is always a
multiple of 8 bits. The MSB is always sent first (for instruction and data bytes).
4. A rising edge on CS
indicates the end of data transmission.
11.6.2 Default modes at start-up
During circuit initialization it does not matter which output data standard has been
selected. At power-up, the device enters Pin control mode.
A falling edge on CS
triggers a transition to SPI control mode. When the ADC1415S
enters SPI control mode, the output data standard (CMOS/LVDS DDR) is determined by
the level on pin SDIO (see Figure 29
). Once in SPI control mode, the output data standard
can be changed via bit LVDS/CMOS in Table 23
.
When the ADC1415S enters SPI control mode, the output data format (two’s complement
or offset binary) is determined by the level on pin SCLK (gray code can only be selected
via the SPI). Once in SPI control mode, the output data format can be changed via bit
DATA_FORMAT[1:0] in Table 23
.
Table 17. Number of data bytes to be transferred after the instruction bytes
W1 W0 Number of bytes transmitted
001 byte
012 bytes
103 bytes
1 1 4 bytes or more
Fig 28. SPI mode timing
SCLK
SDIO
R/W
W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D3 D2 D1 D0D0 D7 D6 D5 D4
Instruction bytes Register N (data) Register N + 1 (data)
005aaa06
2
CS
ADC1415S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 4 — 17 December 2010 30 of 42
NXP Semiconductors
ADC1415S series
Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs
Fig 29. Default mode at start-up: SCLK LOW = offset binary; SDIO HIGH = LVDS DDR
Fig 30. Default mode at start-up: SCLK HIGH = two’s complement; SDIO LOW = CMOS
CS
SDIO
(CMOS LVDS DDR)
SCLK
(Data format)
Offset binary, LVDS DDR
default mode at start-up
005aaa06
3
SDIO
(CMOS LVDS DDR)
SCLK
(Data format)
two's complement, CMOS
default mode at start-up
005aaa06
4
CS
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ADC1415S125/DB,598

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BOARD DEMO FOR ADC1415S125
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