ADC1415S125/DB,598 Datasheet ADC1415S065HN/C1,5, ADC1415S080HN/C1,5, ADC1415S105HN/C1,5 | P31-P33

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Product data sheet Rev. 4 — 17 December 2010 31 of 42

NXP Semiconductors

ADC1415S series

Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs

11.6.3 Register allocation map

Table 18. Register allocation map

Add

Hex

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bin

0005 Reset and

operating mode

R/W SW_RST RESERVED[2:0] - - OP_MODE[1:0] 0000 0000

0006 Clock R/W - - - SE_SEL DIFF_SE - CLKDIV DCS_EN 0000 0001

0008 Internal reference R/W - - - - INTREF_EN INTREF[2:0] 0000 0000

0010 Input buffer R/W - - - - - - IB_IBIAS[1:0] 0000 0011

0011 Output data

standard.

R/W - - - LVDS_

CMOS

OUTBUF OUTBUS_SWAP DATA_FORMAT[1:0] 0000 0000

0012 Output clock R/W - - - - DAVINV DAVPHASE[2:0] 0000 1110

0013 Offset R/W - - DIG_OFFSET[5:0] 0000 0000

0014 Test pattern 1 R/W - - - - - TESTPAT_SEL[2:0] 0000 0000

0015 Test pattern 2 R/W TESTPAT_USER[13:6] 0000 0000

0016 Test pattern 3 R/W TESTPAT_USER[5:0] - - 0000 0000

0017 Fast OTR R/W - - - - FASTOTR FASTOTR_DET[2:0] 0000 0000

0020 CMOS output R/W - - - - DAV_DRV[1:0] DATA_DRV[1:0] 0000 1110

0021 LVDS DDR O/P 1 R/W - - DAVI_x2_

DAVI[1:0] DATAI_x2_EN DATAI[1:0] 0000 0000

0022 LVDS DDR O/P 2 R/W - - - - BIT_BYTE_

WISE

LVDS_INT_TER[2:0] 0000 0000

Product data sheet Rev. 4 — 17 December 2010 32 of 42

NXP Semiconductors

ADC1415S series

Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs

Table 19. Reset and operating mode control register (address 0005h) bit description

Default values are highlighted.

Bit Symbol Access Value Description

7 SW_RST R/W reset digital section

0no reset

1 performs a reset on SPI registers

6 to 4 RESERVED[2:0] 000 reserved

3 to 2 - 00 not used

1 to 0 OP_MODE[1:0] R/W operating mode

00 normal (Power-up)

01 Power-down

10 Sleep

11 normal (Power-up)

Table 20. Clock control register (address 0006h) bit description

Default values are highlighted.

Bit Symbol Access Value Description

7 to 5 - 000 not used

4 SE_SEL R/W single-ended clock input pin select

0CLKM

1CLKP

3 DIFF_SE R/W differential/single ended clock input select

0 fully differential

1 single-ended

2 - 0 not used

1 CLKDIV R/W clock input divide by 2

0disabled

1 enabled

0 DCS_EN R/W duty cycle stabilizer

0 disabled

1 enabled

Product data sheet Rev. 4 — 17 December 2010 33 of 42

NXP Semiconductors

ADC1415S series

Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs

Table 21. Internal reference control register (address 0008h) bit description

Default values are highlighted.

Bit Symbol Access Value Description

7 to 4 - 0000 not used

3 INTREF_EN R/W programmable internal reference enable

0disable

1 active

2 to 0 INTREF[2:0] R/W programmable internal reference

000 0 dB (FS = 2 V)

001 −1dB (FS=1.78V)

010 −2dB (FS=1.59V)

011 −3dB (FS=1.42V)

100 −4dB (FS=1.26V)

101 −5dB (FS=1.12V)

110 −6dB (FS=1V)

111 reserved

Table 22. Input buffer control register (address 0010h) bit description

Default values are highlighted.

Bit Symbol Access Value Description

7 to 2 - 000000 not used

1 to 0 IB_IBIAS[1:0] R/W input buffer bias current

00 not used

01 medium

10 low

11 high

Table 23. Output data standard control register (address 0011h) bit description

Default values are highlighted.

Bit Symbol Access Value Description

7 to 5 - 000 not used

4 LVDS_CMOS R/W output data standard: LVDS DDR or CMOS

0CMOS

1 LVDS DDR

3 OUTBUF R/W output buffers enable

0 output enabled

1 output disabled (high Z)

2 OUTBUS_SWAP R/W output bus swapping

0 no swapping

1 output bus is swapped (MSB becomes LSB and vice versa)

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42

ADC1415S125/DB,598

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ADC1415S125/DB,598

ADC1415S125/DB,598

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