ADC1415S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 4 — 17 December 2010 18 of 42
NXP Semiconductors
ADC1415S series
Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs
11.1.2 Operating mode selection
The active ADC1415S operating mode (Power-up, Power-down or Sleep) can be selected
via the SPI interface (see Table 19
) or using pins PWD and OE in Pin control mode, as
described in Table 10
.
11.1.3 Selecting the output data standard
The output data standard (CMOS or LVDS DDR) can be selected via the SPI interface
(see Table 23
) or using pin ODS in Pin control mode. LVDS DDR is selected when ODS is
HIGH, otherwise CMOS is selected.
11.1.4 Selecting the output data format
The output data format can be selected via the SPI interface (offset binary, two’s
complement or gray code; see Table 23
) or using pin DFS in Pin control mode (offset
binary or two’s complement). Offset binary is selected when DFS is LOW. When DFS is
HIGH, two’s complement is selected.
11.2 Analog inputs
11.2.1 Input stage
The analog input of the ADC1415S supports a differential or a single-ended input drive.
Optimal performance is achieved using differential inputs. The ADC inputs are internally
biased and need to be decoupled.
The full-scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p)
via a programmable internal reference (see Section 11.3
and Table 21).
The equivalent circuit of the input buffer followed by the Sample and Hold (S/H) input
stage, including ElectroStatic Discharge (ESD) protection and circuit and package
parasitics, is shown in Figure 14
.
Table 10. Operating mode selection via pin PWD and OE
Pin PWD Pin OE Operating mode Output high-Z
0 0 Power-up no
0 1 Power-up yes
1 0 Sleep yes
1 1 Power-down yes
