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ADC1415S125/DB,598

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42
ADC1415S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 4 — 17 December 2010 4 of 42
NXP Semiconductors
ADC1415S series
Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs
6. Pinning information
6.1 Pinning
6.2 Pin description
Fig 2. Pin configuration with CMOS digital outputs
selected
Fig 3. Pin configuration with LVDS/DDR digital
outputs selected
005aaa10
2
ADC1415S
HVQFN40
D9
AGND
VDDA3V
D8
INP D7
INM D6
AGND D5
VDDA5V D4
VCM D3
AGND D2
REFT D1
REFB D0
VDDA3V
CLKP
CLKM
DEC
PWD
D13
D12
D11
D10
VREF
SENSE
SDIO/ODS
SCLK/DFS
OTR
OGND
VDDO
n.c.
DAV
10 21
9 22
8 23
7 24
6 25
5 26
4 27
3 28
2 29
1 30
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
terminal 1
index area
Transparent top view
CS
OE
ADC1215S
HVQFN40
D8_D9_M
D8_D9_P
D6_D7_M
D6_D7_P
D4_D5_M
D4_D5_P
D2_D3_M
D2_D3_P
D0_D1_M
D0_D1_P
VDDA3V
INP
INM
AGND
VDDA5V
VCM
AGND
REFT
REFB
VDDA3V
CLKP
CLKM
DEC
PWD
D12_D13_M
D12_D13_P
D10_D11_M
D10_D11_P
VREF
SENSE
SDIO/ODS
SCLK/DFS
OTR
OGND
VDDO
n.c.
DAV
10 21
9 22
8 23
7 24
6 25
5 26
4 27
3 28
2 29
1 30
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
AGND
terminal 1
index area
Transparent top view
005aaa103
OE
CS
Table 2. Pin description (CMOS digital outputs)
Symbol Pin Type
[1]
Description
REFB 1 O bottom reference
REFT 2 O top reference
AGND 3 G analog ground
VCM 4 O common-mode output voltage
VDDA5V 5 P 5 V analog power supply
AGND 6 G analog ground
INM 7 I complementary analog input
INP 8 I analog input
AGND 9 G analog ground
VDDA3V 10 P 3 V analog power supply
VDDA3V 11 P 3 V analog power supply
CLKP 12 I clock input
CLKM 13 I complementary clock input
DEC 14 O regulator decoupling node
OE
15 I output enable, active LOW
PWD 16 I power down, active HIGH
ADC1415S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 4 — 17 December 2010 5 of 42
NXP Semiconductors
ADC1415S series
Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs
[1] P: power supply; G: ground; I: input; O: output; I/O: input/output.
D13 17 O data output bit 13 (Most Significant Bit (MSB))
D12 18 O data output bit 12
D11 19 O data output bit 11
D10 20 O data output bit10
D9 21 O data output bit 9
D8 22 O data output bit 8
D7 23 O data output bit 7
D6 24 O data output bit 6
D5 25 O data output bit 5
D4 26 O data output bit 4
D3 27 O data output bit 3
D2 28 O data output bit 2
D1 29 O data output bit 1
D0 30 O data output bit 0 (Least Significant Bit (LSB))
DAV 31 O data valid output clock
n.c. 32 - not connected
VDDO 33 P output power supply
OGND 34 G output ground
OTR 35 O out of range
SCLK/DFS 36 I SPI clock / data format select
SDIO/ODS 37 I/O SPI data IO / output data standard
CS
38 I SPI chip select
SENSE 39 I reference programming pin
VREF 40 I/O voltage reference input/output
Table 3. Pin description (LVDS DDR) digital outputs)
Symbol Pin
[1]
Type
[2]
Description
D12_D13_M 17 O differential output data D12 and D13 multiplexed, complement
D12_D13_P 18 O differential output data D12 and D13 multiplexed, true
D10_D11_M 19 O differential output data D10 and D11 multiplexed, complement
D10_D11_P 20 O differential output data D10 and D11 multiplexed, true
D8_D9_M 21 O differential output data D8 and D9 multiplexed, complement
D8_D9_P 22 O differential output data D8 and D9 multiplexed, true
D6_D7_M 23 O differential output data D6 and D7 multiplexed, complement
D6_D7_P 24 O differential output data D6 and D7 multiplexed, true
D4_D5_M 25 O differential output data D4 and D5 multiplexed, complement
D4_D5_P 26 O differential output data D4 and D5 multiplexed, true
D2_D3_M 27 O differential output data D2 and D3 multiplexed, complement
D2_D3_P 28 O differential output data D2 and D3 multiplexed, true
D0_D1_M 29 O differential output data D0 and D1 multiplexed, complement
Table 2. Pin description (CMOS digital outputs)
…continued
Symbol Pin Type
[1]
Description
ADC1415S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 4 — 17 December 2010 6 of 42
NXP Semiconductors
ADC1415S series
Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs
[1] Pins 1 to 16 and pins 33 to 40 are the same for both CMOS and LVDS DDR outputs (see Table 2)
[2] P: power supply; G: ground; I: input; O: output; I/O: input/output.
7. Limiting values
8. Thermal characteristics
[1] Value for six layers board in still air with a minimum of 25 thermal vias.
D0_D1_P 30 O differential output data D0 and D1 multiplexed, true
DAVM 31 O data valid output clock, complement
DAVP 32 O data valid output clock, true
Table 3. Pin description
…continued (LVDS DDR) digital outputs)
Symbol Pin
[1]
Type
[2]
Description
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
O
output voltage pins D13 to D0 or
pins D12_D13_P to D0_D1_P
and D12_D13_M to D0_D1_M
−0.4 +3.9 V
V
DDA(3V)
analog supply
voltage 3 V
on pin VDDA3V −0.4 +4.6 V
V
DDA(5V)
analog supply
voltage 5 V
on pin VDDA5V −0.5 +6.0 V
V
DDO
output supply voltage −0.4 +4.6 V
T
stg
storage temperature −55 +125 °C
T
amb
ambient temperature −40 +85 °C
T
j
junction temperature - 125 °C
Table 5. Thermal characteristics
Symbol Parameter Conditions Typ Unit
R
th(j-a)
thermal resistance from junction to ambient
[1]
30.5 K/W
R
th(j-c)
thermal resistance from junction to case
[1]
13.3 K/W
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42

ADC1415S125/DB,598

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Buy ADC1415S125/DB,598
Manufacturer:
NXP Semiconductors
Description:
BOARD DEMO FOR ADC1415S125
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