ADC1415S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 4 — 17 December 2010 24 of 42
NXP Semiconductors
ADC1415S series
Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs
11.4.2 Equivalent input circuit
The equivalent circuit of the input clock buffer is shown in Figure 24. The common-mode
voltage of the differential input stage is set via internal 5 kΩ resistors.
Single-ended or differential clock inputs can be selected via the SPI interface
(see Table 20
). If single-ended is enabled, the input pin (CLKM or CLKP) is selected via
control bit SE_SEL.
If single-ended is implemented without setting bit SE_SEL to the appropriate value, the
unused pin should be connected to ground via a capacitor.
11.4.3 Duty cycle stabilizer
The duty cycle stabilizer can improve the overall performance of the ADC by
compensating the duty cycle of the input clock signal. When the duty cycle stabilizer is
active (bit DCS_EN = logic 1; see Table 20
), the circuit can handle signals with duty
cycles of between 30 % and 70 % (typical). When the duty cycle stabilizer is disabled
(DCS_EN = logic 0), the input clock signal should have a duty cycle of between 45 % and
55 %.
11.4.4 Clock input divider
The ADC1415S contains an input clock divider that divides the incoming clock by a factor
of 2 (when bit CLKDIV = logic 1; see Table 20
). This feature allows the user to deliver a
higher clock frequency with better jitter performance, leading to a better SNR result once
acquisition has been performed.
V
cm(clk)
= common-mode voltage of the differential input stage.
Fig 24. Equivalent input circuit
CLKP
CLKM
005aaa05
Package ESD Parasitics
5 kΩ 5 kΩ
V
cm(clk)
SE_SEL SE_SEL
