M24C64-DF, M24C64-W, M24C64-R, M24C64-F Signal description
Doc ID 16891 Rev 26 11/44
Figure 7. I
2
C bus protocol
Table 2. Device select code
Device type identifier
(1)
1. The most significant bit, b7, is sent first.
Chip Enable address
(2)(3)
2. E2, E1 and E0 are compared against the respective external pins on the memory device.
3. For the WLCSP package, the (E2,E1,E0) inputs are internally connected to (0,0,1).
RW
b7 b6 b5 b4 b3 b2 b1 b0
Device select code1010E2E1E0RW
Table 3. Address most significant byte
b15 b14 b13 b12 b11 b10 b9 b8
Table 4. Address least significant byte
b7 b6 b5 b4 b3 b2 b1 b0
SCL
SDA
SCL
SDA
SDA
Start
Condition
SDA
Input
SDA
Change
AI00792B
Stop
Condition
1 23 7 89
MSB
ACK
Start
Condition
SCL
1 23 7 89
MSB ACK
Stop
Condition
