DC and AC parameters M24C64-DF, M24C64-W, M24C64-R, M24C64-F
30/44 Doc ID 16891 Rev 26
Table 17. 400 kHz AC characteristics
Symbol Alt. Parameter
(1)
1. Test conditions (in addition to those in Table 7, Table 8, Ta ble 9 and Table 10).
Min. Max. Unit
f
C
f
SCL
Clock frequency - 400 kHz
t
CHCL
t
HIGH
Clock pulse width high 600 - ns
t
CLCH
t
LOW
Clock pulse width low 1300 ns
t
QL1QL2
(2)
2. Characterized value, not tested in production.
t
F
SDA (out) fall time 20
(3)
3. With C
L
= 10 pF.
120 ns
t
XH1XH2
t
R
Input signal rise time
(4)
4. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when
f
C
< 400 kHz.
(4)
ns
t
XL1XL2
t
F
Input signal fall time
(4) (4)
ns
t
DXCX
t
SU:DAT
Data in set up time 100 - ns
t
CLDX
t
HD:DAT
Data in hold time 0 - ns
t
CLQX
t
DH
Data out hold time 100
(5)
5. The new M24C64 device (identified by the process letter K) offers t
CLQX
= 100 ns (min) and t
CLQV
= 100 ns
(min), while the current device offers t
CLQX
= 200 ns (min) and t
CLQV
= 200 ns (min). Both series offer a
safe margin compared to the I
2
C specification which recommends t
CLQV
= 0 ns (min).
-ns
t
CLQV
(6)(7)
6. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
7. t
CLQV
is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 V
CC
or
0.7 V
CC
, assuming that R
bus
× C
bus
time constant is within the values specified in Figure 5.
t
AA
Clock low to next data valid (access time) 100
(5)
900 ns
t
CHDL
t
SU:STA
Start condition setup time 600 - ns
t
DLCL
t
HD:STA
Start condition hold time 600 - ns
t
CHDH
t
SU:STO
Stop condition set up time 600 - ns
t
DHDL
t
BUF
Time between Stop condition and next Start
condition
1300 - ns
t
WLDL
(8)(2)
8. WC=0 set up time condition to enable the execution of a WRITE command.
t
SU:WC
WC set up time (before the Start condition) 0 - µs
t
DHWH
(9)(2)
9. WC=0 hold time condition to enable the execution of a WRITE command.
t
HD:WC
WC hold time (after the Stop condition) 1 - µs
t
W
t
WR
Write time - 5 ms
t
NS
(2)
Pulse width ignored (input filter on SCL and
SDA) - single glitch
-80
(10)
10. The current M24C64 device offers t
NS
=100 ns (max), the new M24C64 device (identified by the process
letter K) offers t
NS
=80 ns (max). Both products offer a safe margin compared to the 50 ns minimum value
recommended by the I
2
C specification.
ns
