M24C64-DF, M24C64-W, M24C64-R, M24C64-F Device operation
Doc ID 16891 Rev 26 19/44
Figure 11. Write cycle polling flowchart using ACK
4.12 Minimizing system delays by polling on ACK
During the internal Write cycle, the device disconnects itself from the bus, and writes a copy
of the data from its internal latches to the memory cells. The maximum Write time (t
w
) is
shown in
Ta b le 1 7 , but the typical time is shorter. To make use of this, a polling sequence can
be used by the bus master.
The sequence, as shown in Figure 11, is:
1. Initial condition: a Write cycle is in progress.
2. Step 1: the bus master issues a Start condition followed by a device select code (the
first byte of the new instruction).
3. Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and
the bus master goes back to Step 1. If the device has terminated the internal Write
cycle, it responds with an Ack, indicating that the device is ready to receive the second
part of the instruction (the first byte of this instruction having been sent during Step 1).
Write cycle
in progress
AI01847d
Next
operation is
addressing the
memory
Start condition
Device select
with RW = 0
ACK
Returned
YES
NO
YESNO
ReStart
Stop
Data for the
Write operation
Device select
with RW = 1
Send address
and receive ACK
First byte of instruction
with RW = 0 already
decoded by the device
YESNO
Start
condition
Continue the
Write operation
Continue the
Random Read operation
Device operation M24C64-DF, M24C64-W, M24C64-R, M24C64-F
20/44 Doc ID 16891 Rev 26
Figure 12. Read mode sequences
1. The seven most significant bits of the device select code of a Random Read (in the 1
st
and 4
th
bytes) must
be identical.
Start
Dev select * Byte address Byte address
Start
Dev select Data out 1
AI01105d
Data out N
Stop
Start
Current
Address
Read
Dev select Data out
Random
Address
Read
Stop
Start
Dev select * Data out
Sequential
Current
Read
Stop
Data out N
Start
Dev select * Byte address Byte address
Sequential
Random
Read
Start
Dev select * Data out 1
Stop
ACK
R/W
NO ACK
ACK
R/W
ACK ACK ACK
R/W
ACK ACK ACK NO ACK
R/W
NO ACK
ACK ACK ACK
R/W
ACK ACK
R/W
ACK NO ACK
M24C64-DF, M24C64-W, M24C64-R, M24C64-F Device operation
Doc ID 16891 Rev 26 21/44
4.13 Read operations
Read operations are performed independently of the state of the Write Control (WC) signal.
After the successful completion of a Read operation, the device’s internal address counter is
incremented by one, to point to the next byte address.
4.14 Random Address Read
A dummy Write is first performed to load the address into this address counter (as shown in
Figure 12) but without sending a Stop condition. Then, the bus master sends another Start
condition, and repeats the device select code, with the Read/Write
bit (RW) set to 1. The
device acknowledges this, and outputs the contents of the addressed byte. The bus master
must not acknowledge the byte, and terminates the transfer with a Stop condition.
4.15 Current Address Read
For the Current Address Read operation, following a Start condition, the bus master only
sends a device select code with the Read/Write
bit (RW) set to 1. The device acknowledges
this, and outputs the byte addressed by the internal address counter. The counter is then
incremented. The bus master terminates the transfer with a Stop condition, as shown in
Figure 12, without acknowledging the Byte.
4.16 Sequential Read
This operation can be used after a Current Address Read or a Random Address Read. The
bus master does acknowledge the data byte output, and sends additional clock pulses so
that the device continues to output the next byte in sequence. To terminate the stream of
bytes, the bus master must not acknowledge the last byte, and must generate a Stop
condition, as shown in Figure 12.
The output data comes from consecutive addresses, with the internal address counter
automatically incremented after each byte output. After the last memory address, the
address counter ‘rolls-over’, and the device continues to output data from memory
address 00h.
4.17 Read Identification Page (M24C64-D)
The Identification Page (32 bytes) is an additional page which can be written and (later)
permanently locked in Read-only mode.
The Identification Page can be read by issuing an Read Identification Page instruction. This
instruction uses the same protocol and format as the Random Address Read (from memory
array) with device type identifier defined as 1011b. The MSB address bits A15/A5 are don't
care, the LSB address bits A4/A0 define the byte address inside the Identification Page. The
number of bytes to read in the ID page must not exceed the page boundary, otherwise
unexpected data is read (e.g.: when reading the Identification Page from location 10d, the
number of bytes should be less than or equal to 22, as the ID page boundary is 32 bytes).

M24C64-FMB6TG

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
EEPROM 128 Kbit 64 Kbit 1.7 V to 5.5 V
Lifecycle:
New from this manufacturer.
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